mcuad.v

FPGA verilog

module MCUAD
	(
		EN,
		WR,
		SYS_CLK,
		AddrBus,
		ADData,
		OutputPwr,
		REFLECT_K_Set,
		REFLECT_B_Set,
		REFLECTOutput
	);
	`include "Parameter.v"
	
	input					EN;
	input					WR;
	input					SYS_CLK;
	input	[12:0]			AddrBus;
	input	[11:0]			ADData;
	input	[31:0]			OutputPwr;
	input 	[31:0]			REFLECT_K_Set,
							REFLECT_B_Set;

	output	[31:0]			REFLECTOutput;
							
	reg		[31:0]			REFLECTOutput;
	
	reg		[31:0]			OutputPwrReg;
	wire	[31:0]			McuParam;
	wire	[31:0]			RelectionPwr;
	
	
	K_BCalculator ReflectCalculator(
								.K(REFLECT_K_Set),
								.B(REFLECT_B_Set),
								.X(ADData),
								.result(McuParam));
	lpm_sub0 	Reflect_Sub(.dataa(OutputPwrReg),
						.datab(McuParam),
						.result(RelectionPwr));
	
	always @(posedge SYS_CLK)
	begin
		if (EN&&(WR||(AddrBus!=REFLECT_AD)))
			OutputPwrReg <= OutputPwr;
	end
	
	always @(negedge WR)
	begin
		if (AddrBus==REFLECT_AD)
			REFLECTOutput <= RelectionPwr;
	end
	
endmodule