overalarmmonitor.v

FPGA verilog

module OverAlarmMonitor
	(
		EN,
		SYS_CLK,
		Param,
		Debounce_Time_Set,
		THR_Set,
		Alarm_Output
	);
	input 			EN;
	input 			SYS_CLK;
	input	[31:0]	Param,
					THR_Set;
	input	[31:0]	Debounce_Time_Set;
	output 			Alarm_Output;
	
	reg 			AlarmReg;
	wire			Alarm;
//	reg				ResumeAlarm;
	reg		[31:0]	RaiseTime,ResumeTime;
	
	assign Alarm_Output = AlarmReg;
	
	assign 	Alarm = Param > THR_Set;
	
	always @(posedge SYS_CLK)
	begin
		if (EN)
		begin
			if (Alarm)
			begin
				if (RaiseTime[31]!=1)
					RaiseTime <= RaiseTime + 1'b1;
			end
			else if (ResumeTime>32'd2)
				RaiseTime <= 32'h00000000;
		end
		else
			RaiseTime <= 32'h00000000;
	end

	always @(posedge SYS_CLK)
	begin
		if (EN)
		begin
			if (!Alarm)
			begin
				if (ResumeTime[31]!=1)
					ResumeTime <= ResumeTime + 1'b1;
			end
			else if (RaiseTime>32'd2)
				ResumeTime <= 32'h00000000;
		end
		else
			ResumeTime <= 32'h00000000;
	end
	
	always @(posedge SYS_CLK)
	begin
		if (EN)
		begin
			if (Alarm)
			begin
				if (RaiseTime>Debounce_Time_Set)
					AlarmReg <= 1'b1;
			end
			else begin
				if (ResumeTime>Debounce_Time_Set)
					AlarmReg <= 1'b0;
			end
		end
		else
			AlarmReg <= 1'b0;
	end
	
endmodule