reflectfilter.v

FPGA verilog

module ReflectFilter
	(
		CLK,
		InputData,
		OutputData
	);

	input				CLK;
	input	[31:0]		InputData;
	output	[31:0]		OutputData;
	
	wire	[34:0]	AccResult;
	wire	[31:0]	ParamResult;
		

	reg		[11:0]	Input0,Input1,Input2,Input3;
	
	lpm_acc0 ParamAcc(.clock(CLK),
						.data(ParamResult),
						.result(AccResult));
	
	lpm_sub4 ParamSub(.dataa({1'b0,InputAD}),
						.datab({1'b0,Input3}),
						.result(ParamResult));
	
	assign OutputAD = AccResult[14:3];
	
	always @(posedge CLK)
	begin
		Input0 <= InputAD;
		Input1 <= Input0;
		Input2 <= Input1;
		Input3 <= Input2;
	end
	
endmodule