dopalarmmonitor.v

FPGA verilog

module DOPAlarmMonitor
	(
		EN,
		AlarmEN,
		SYS_CLK,
		Param,
		Debounce_Time_Set,
		LOP_THR_HI_Set,
		LOP_THR_LO_Set,
		LOP_HYS_HI_Set,
		LOP_HYS_LO_Set,
		Alarm_Output
	);

	input			EN;
	input			AlarmEN;
	input 			SYS_CLK;
	input	[31:0]	Param,
					LOP_THR_HI_Set,
					LOP_THR_LO_Set,
					LOP_HYS_HI_Set,
					LOP_HYS_LO_Set;
										
	input	[31:0]	Debounce_Time_Set;
	output 			Alarm_Output;
	
	reg 			AlarmReg;
	wire			Alarm;
	wire			ResumeAlarm;
	
	reg		[31:0]	RaiseTime,ResumeTime;
	
	
	assign Alarm = (Param>LOP_THR_HI_Set)||(Param<LOP_THR_LO_Set);

	assign ResumeAlarm = (Param<LOP_HYS_HI_Set)&&(Param>LOP_HYS_LO_Set);

	assign Alarm_Output = AlarmReg;
	
	always @(posedge SYS_CLK)
	begin
		if (Alarm)
		begin
			if (RaiseTime[31]!=1)
				RaiseTime <= RaiseTime + 1'b1;
		end
		else if (ResumeTime>32'd9)
			RaiseTime <= 32'h00000000;
	end

	always @(posedge SYS_CLK)
	begin
		if (!Alarm)
		begin
			if (ResumeTime[31]!=1)
				ResumeTime <= ResumeTime + 1'b1;
		end
		else if (RaiseTime>32'd9)
			ResumeTime <= 32'h00000000;
	end
	
	always @(posedge SYS_CLK)
	begin
		if (EN)
		begin
			if (AlarmEN)
			begin
				if (Alarm)
				begin
					if (RaiseTime>32'd400000)
						AlarmReg <= 1'b1;
				end
				else begin
					if (ResumeAlarm)
					begin
						if (ResumeTime>Debounce_Time_Set)
							AlarmReg <= 1'b0;
					end
				end
			end
			else
				AlarmReg <= 1'b0;
		end
	end
endmodule