ramp.v

FPGA verilog

module RAMP
(
	//input
	EN,
	SYS_CLK,
	OpMode,
	RAMP_TIME_Set,
//	ISP_AUTO_Set,
	RampStart,
	OutputLim,
	GAIN_SET_Set,
	PWR_SET_Set,
	EYESAFE_PWR_Set,
	CURR_SET_Set,
	Gain,
	OutputPwrAsmW,
	POutsig,
	Pump_DacData, 
	VOA_DacData, 
	//output
	Pump_DacOut, 
//	VOA_DacOut,
	RampOut
);
	input			EN;
	input			SYS_CLK;
//	input			ISP_AUTO_Set;
	input	[2:0]	OpMode;
	input			RampStart;
	input			OutputLim;
	input	[11:0]	CURR_SET_Set,
					Pump_DacData,
					VOA_DacData;
	input 	[31:0]	GAIN_SET_Set,
					PWR_SET_Set,
					RAMP_TIME_Set,
					EYESAFE_PWR_Set,
					Gain,
					OutputPwrAsmW,
					POutsig;
					
	output 	[11:0] 	Pump_DacOut;
	//output 	[11:0] 	VOA_DacOut;
	output			RampOut;

	reg	 	[11:0] 	Pump_DacOut;
//	reg	 	[11:0] 	VOA_DacOut;

	
	wire			ACCCtrl;
	wire			PumpDown;

	reg		[2:0]	OldMode;
	
	reg				Ramp;
	
	reg		[11:0]	CurrPumpDac;
	
	reg		[31:0]	TimeCounter;
	
	reg		[11:0]	Pump_DacOutSaved;
	reg		[31:0]	Target,Now;
	reg		[31:0]	TargetReg;
	reg				RampUpReg;
	
	
	`include "Parameter.v"
	
	
	assign RampOut = Ramp;
	
	assign 	ACCCtrl = OldMode==ACC_MODE;
	assign 	PumpDown = OldMode==PD_MODE;
	
	always @(OpMode or 
			GAIN_SET_Set or
			EYESAFE_PWR_Set or
			PWR_SET_Set or 			
			CURR_SET_Set)
	begin
		case (OpMode)
			AGC_MODE: 	Target = GAIN_SET_Set;
			APR_MODE:	Target = EYESAFE_PWR_Set;
			APC_MODE:	Target = PWR_SET_Set;
			ACC_MODE:	Target = {20'h00000,CURR_SET_Set};
			default:	Target = 0;
		endcase
	end
	
	always @(OldMode or 
			Gain or
			OutputPwrAsmW or 
			POutsig or
			Pump_DacOutSaved)
	begin
		case (OldMode)
			AGC_MODE: 	Now = Gain;
			APR_MODE:	Now = OutputPwrAsmW;
			APC_MODE:	Now = POutsig;
			ACC_MODE:	Now = {20'h00000,Pump_DacOutSaved};
			default:	Now = 32'd0;
		endcase
	end

	always @(posedge SYS_CLK)
	begin
		if (RampStart)
		begin
			OldMode<=OpMode;
			TargetReg <= Target;
			if (Now>Target)
				RampUpReg <= 1'b0;
			else
				RampUpReg <= 1'b1;
			CurrPumpDac <= Pump_DacOutSaved;
			Ramp <= 1'b1;
			TimeCounter <= 32'h00000000;				
		end
		else if (Ramp)
		begin
			if (TimeCounter<RAMP_TIME_Set)
				TimeCounter <= TimeCounter+ 1'b1;
			else begin
				if (OutputLim)
					Ramp <= 1'b0;
				else begin
					if (RampUpReg)
					begin
						if ((CurrPumpDac<12'hFFF)&&(Now<TargetReg))
							CurrPumpDac <= CurrPumpDac + 1'b1;
						else
							Ramp <= 1'b0;
					end
					else begin
						if ((CurrPumpDac>12'h000)&&(Now>TargetReg))
							CurrPumpDac <= CurrPumpDac - 1'b1;
						else
							Ramp <= 1'b0;
					end
				end
				TimeCounter <= 32'h00000000;
			end
		end
	end
	
	always @(posedge SYS_CLK)
	begin
		Pump_DacOutSaved <= Pump_DacOut;
	end
	
	always @(RampStart or Ramp or ACCCtrl or OpMode or PumpDown or CurrPumpDac or Pump_DacData or CURR_SET_Set or Pump_DacOutSaved)
	begin
		if (!RampStart)
		begin
			if (Ramp)
				Pump_DacOut = CurrPumpDac;
			//else if (ACCCtrl&&(!ISP_AUTO_Set))
			//	Pump_DacOut = CURR_SET_Set;
			else if (PumpDown)
				Pump_DacOut = 12'd0;
			else
				Pump_DacOut = Pump_DacData;
		end
		else
			Pump_DacOut = Pump_DacOutSaved;
	end

endmodule