modectrl.v

FPGA verilog

module ModeCtrl(
		CLK,
		EN,
		OP_MODE_Set,
		LOSMODE_Set,
		AUTO_MUTE_Set,
		APC_KP_Set,
		APC_KI_Set,
		PLIM_Set,
		GLIM_Set,
		AGC_KP_Set,
		AGC_KI_Set,
		ISP_AUTO_Set,
		CURR_SET_Set,
		TARGET_GAIN_Set,
		TARGET_PWR_Set,
		EYESAFE_PWR_Set,
		MUTEON_Set,
		PUMPON_Set,	
		Pump_Protect_Alarm,
		Ramp,
		Input_LOS_Alarm,
		Reflection_Alarm,
		Amplifier_Disable_Input,
		Output_Mute_Input,
		OutputPwrAsmW,
		Gain,
		POutsig,
		FeedForwardData,
		OpModeOut,
		PumpDown,
		RampStart,
		Mst,
		OutputLim,
		Pump_DacData
);
	`include "parameter.v"
	input	CLK;
	input	EN;
	input	Amplifier_Disable_Input;
	input	Output_Mute_Input;
	input	Pump_Protect_Alarm;
	input	Ramp;
	input	Input_LOS_Alarm;
	input	Reflection_Alarm;
	input	AUTO_MUTE_Set;
	input	ISP_AUTO_Set;
	input	[11:0]	CURR_SET_Set;
	input	MUTEON_Set;
	input	PUMPON_Set;	
	input	[1:0]	LOSMODE_Set;
	input	[1:0]	OP_MODE_Set;
	input	[31:0]	APC_KP_Set,
					APC_KI_Set,
					PLIM_Set,
					GLIM_Set,
					AGC_KP_Set,
					AGC_KI_Set,
					TARGET_GAIN_Set,
					TARGET_PWR_Set,
					EYESAFE_PWR_Set;
	
	input	[31:0] 	Gain,
					OutputPwrAsmW,
					POutsig;
	input	[11:0]	FeedForwardData;
					
	output	[1:0] 	OpModeOut;
	output			PumpDown;
	output			RampStart;
	output	[2:0]	Mst;
	output			OutputLim;
	output	[11:0] 	Pump_DacData;
			
	reg				PumpDown;
	reg				RampStart;
	reg		[31:0] 	Ki;
	reg		[31:0] 	Kp;
	reg		[31:0] 	NextPoint;
	reg		[31:0] 	TargetReg;
	reg		[31:0] 	CompareTarget;
	reg		[11:0]	Pump_DacOutSaved;	
	wire	[11:0] 	Pump_DacSignal;

	
	wire		FeedForwardEN;
	wire		Amplifier_Disable_Input_Single;
	wire		Output_Mute_Input_Single;
	
	wire		Lim_Signal,Dis_Signal,Es_Signal;	
	
	reg [1:0]	OpMode,NextMode,OrgOpMode;
	
	reg	[21:0]	LimCounter;
	reg			LimReg;
	reg	[5:0]	TimeCounter;
	
	reg			ESReg;
	reg	[21:0]	ESCounter;
	
	wire		APREN;
	
	wire   		GainOver,APROver,POutOver;
	
	wire		isAGCMode;
	wire		Idle;
	wire		isACCMode;
	wire		PIDEN;
	
	reg			Updating;
	
	wire	[31:0]	DBTime;
	
	assign Pump_DacData = Pump_DacOutSaved;
	
	assign Idle = Input_LOS_Alarm&(OpMode==AGC_MODE)&(LOSMODE_Set==LM_AGC_IDLE);
	
	assign  DBTime = (isACCMode)?32'd10:32'd1000;
	
	assign 	OutputLim = GainOver|POutOver|Es_Signal;
	
	assign 	isACCMode = OpMode==ACC_MODE;
	
	assign  PIDEN = (OpMode!=PD_MODE)&(OpMode!=ACC_MODE);
	
	assign	OpModeOut = OpMode;

	assign Lim_Signal =LimReg;//
	assign Dis_Signal = (OpMode==PD_MODE);
	assign Es_Signal =  APREN&APROver;
	assign Mst = {Dis_Signal,ESReg,Lim_Signal};
	
	assign  FeedForwardEN  = (isAGCMode);
	assign 	isAGCMode = OrgOpMode==AGC_MODE;

	assign  APREN = Output_Mute_Input_Single||Reflection_Alarm&&AUTO_MUTE_Set||MUTEON_Set;

	InputFilter Amplifier_Disable_KeyFilter(
				.CLK(CLK),
				.KeyInput(Amplifier_Disable_Input),
				.KeyOutput(Amplifier_Disable_Input_Single));

	InputFilter Output_Mute_KeyFilter(
				.CLK(CLK),
				.KeyInput(Output_Mute_Input),
				.KeyOutput(Output_Mute_Input_Single));

	PIDTune	modePIDTune(
			.EN(EN&PIDEN),
			.FeedForwardEN(FeedForwardEN),
			.FeedForwardData(FeedForwardData),
			.CLK(CLK),
			.Ki(AGC_KI_Set),
			.Kp(AGC_KP_Set),
			.NextPoint(NextPoint),
			.Target(TargetReg),
			.PIDResult(Pump_DacSignal));


OverAlarmMonitor GainOverMonitor(
				.EN(EN),
				.SYS_CLK(CLK),
				.Param(Gain),
				.Debounce_Time_Set(DBTime),
				.THR_Set(GLIM_Set),
				.Alarm_Output(GainOver));

OverAlarmMonitor POutOverMonitor(
				.EN(EN),
				.SYS_CLK(CLK),
				.Param(OutputPwrAsmW),
				.Debounce_Time_Set(DBTime),
				.THR_Set(PLIM_Set),
				.Alarm_Output(POutOver));

OverAlarmMonitor APROverMonitor(
				.EN(EN),
				.SYS_CLK(CLK),
				.Param(OutputPwrAsmW),
				.Debounce_Time_Set(DBTime),
				.THR_Set(EYESAFE_PWR_Set),
				.Alarm_Output(APROver));

	always @(posedge CLK)
	begin
		if  (Es_Signal)
		begin
			ESReg <= 1'b1;
			ESCounter <= 21'b0;
		end
		else begin
			if (ESCounter[21])
				ESReg <= 1'b0;
			else
				ESCounter <= ESCounter + 1'b1;
		end
	end

	always @(posedge CLK)
	begin
		if  (POutOver|GainOver)
		begin
			LimReg <= 1'b1;
			LimCounter <= 21'b0;
		end
		else begin
			if (LimCounter[21])
				LimReg <= 1'b0;
			else
				LimCounter <= LimCounter + 1'b1;
		end
	end
	
	always @(posedge CLK)
	begin
		if (NextMode==PD_MODE)
			PumpDown = 1'b1; 
		else
			PumpDown = 1'b0; 
	end

	always @(posedge CLK)
	begin
		if (EN)
		begin
			case (OpMode)
				AGC_MODE:	begin
								if ((!Idle)||Es_Signal)
									Pump_DacOutSaved <= Pump_DacSignal;
							end
				APC_MODE:	Pump_DacOutSaved <= Pump_DacSignal;
				ACC_MODE:	Pump_DacOutSaved <= TargetReg[11:0];
				default:	Pump_DacOutSaved <= 12'h000;
			endcase
		end
	end
	
	always @(posedge CLK)
	begin
		if (OpMode == NextMode)
		begin
			if (isACCMode)
			begin
				if (TimeCounter[5])
				begin
					if (OutputLim)
					begin
						if (TargetReg >32'd0)
							TargetReg <= TargetReg - 1'b1;
					end
					else begin
						if (TargetReg < CompareTarget)
							TargetReg <= TargetReg + 1'b1;
						else if (TargetReg>CompareTarget)
							TargetReg <= TargetReg - 1'b1;
						else
							TargetReg <= CompareTarget;
					end
					TimeCounter <= 6'b00000;
				end
				else
					TimeCounter <= TimeCounter + 1'b1;
			end
			else begin
				if (OutputLim)
				begin
					if (TargetReg >32'd1)
						TargetReg <= TargetReg - 2'b10;
				end
				else begin
					if (Updating) 
					begin
						TargetReg <= CompareTarget;
						Updating <= 1'b0;
					end
					else begin
						if (TargetReg[31:2]<CompareTarget[31:2])
							TargetReg <= TargetReg + 3'b100;
						else if (TargetReg[31:2]>CompareTarget[31:2])
							TargetReg <= TargetReg - 3'b100;
						else begin
							TargetReg <= CompareTarget;
							Updating <= 1'b0;
						end
					end
				end
			end
		end
		else begin
			OpMode <= NextMode;
			case (NextMode)
				AGC_MODE:	begin
								TargetReg <= Gain;
								Updating <= 1'b1;
							end
				APC_MODE:	begin
								TargetReg <= POutsig;
								Updating <= 1'b0;
							end
				ACC_MODE:	begin
								TargetReg <= {20'h00000,Pump_DacOutSaved};
								Updating <= 1'b0;
							end
				default:	begin
								TargetReg <= 0;
								Updating <= 1'b0;
							end
			endcase
			if ((NextMode!=ACC_MODE)&&(NextMode!=PD_MODE))
				OrgOpMode <= NextMode;
		end
	end
	
	wire	[1:0]	AutoSetMode;
	
	assign AutoSetMode = ((OP_MODE_Set==ACC_MODE)&ISP_AUTO_Set&(OrgOpMode!=PD_MODE))?OrgOpMode:OP_MODE_Set;
	
    always @(Amplifier_Disable_Input_Single or 
			PUMPON_Set or 
			Input_LOS_Alarm or 
			LOSMODE_Set or 
			AutoSetMode or
			Pump_Protect_Alarm or
			OP_MODE_Set) 
	begin
		if (Amplifier_Disable_Input_Single||OP_MODE_Set==PD_MODE||
			(!PUMPON_Set)||Pump_Protect_Alarm)
			NextMode = PD_MODE;
		else if (Input_LOS_Alarm)
		begin
			if (OP_MODE_Set==AGC_MODE)
			begin
				if (LOSMODE_Set==LM_AGC_DIS)
					NextMode = PD_MODE;
				else
					NextMode = AutoSetMode;
			end
			else begin
				if (LOSMODE_Set==LM_NO_EFFECT)
					NextMode = AutoSetMode;
				else
					NextMode = PD_MODE;
			end
		end
		else
			NextMode = AutoSetMode;
	end

	always @(OpMode or
			TARGET_GAIN_Set or
			TARGET_PWR_Set or 
			CURR_SET_Set)
	begin
		case (OpMode)
			AGC_MODE: CompareTarget = TARGET_GAIN_Set;
			APC_MODE: CompareTarget = TARGET_PWR_Set;
			ACC_MODE: CompareTarget = {20'h00000,CURR_SET_Set};
			default:  CompareTarget = 0;
		endcase
	end
	
	always @(OpMode or
			Gain or
			POutsig)
	begin
		if (OpMode==AGC_MODE)
		begin
			NextPoint = Gain;
		end
		else begin
			NextPoint = POutsig;
		end
	end
	
endmodule