ildm.v

FPGA verilog

module Pump
	(
		CLK,
		PumpDown,
		Ild1,
		Ild2,
		Hrs1,
		Hrs2,
		Ildm1,
		Ildm2
	);

	input			CLK;
	input			PumpDown;
	input	[31:0]	Ild1;
	input	[31:0]	Ild2;
	output	[31:0]	Hrs1;
	output	[31:0]	Hrs2;
	output	[31:0]	Ildm1;
	output	[31:0]	Ildm2;
	
	reg		[26:0]	MReg;
	
	reg				NReg;
	
	reg		[31:0]	Hrs1Reg,Hrs2Reg;

	reg		[15:0]	Ild1Reg0,Ild1Reg1;
	reg		[15:0]	Ild2Reg0,Ild2Reg1;

	reg		[31:0]	Ildm1Reg1;
	reg		[31:0]	Ildm2Reg1;
	
	wire	[30:0]	denom;
	wire	[39:0]	numer;
	wire	[39:0]	AvgIld;
	reg		[39:0]	IldSum1,IldSum2;

	wire	[39:0]	Sum1,Sum2;
	
	wire	aSecond,AccEN;
	
	assign	aSecond = MReg==26'd19999999;
	assign  AccEN = aSecond&(~PumpDown);
	
	assign  Hrs1 = Hrs1Reg;
	assign  Hrs2 = Hrs2Reg;
	assign  Ildm1 = Ildm1Reg1;
	assign  Ildm2 = Ildm2Reg1;

	lpm_add40 ildacc(.dataa(),
					 .datab(),
					 .result()
	 				);


	lpm_acc2 Ild1Acc(
				.clock(CLK),
				.clken(AccEN),
				.data(Ild1Reg1),
				.result(Sum1));

	lpm_acc2 Ild2Acc(
				.clock(CLK),
				.clken(AccEN),
				.data(Ild2Reg1),
				.result(Sum2));

	lpm_divide2 Ildmdiv(
				.clock(CLK),
				.denom(denom),
				.numer(numer),
				.quotient(AvgIld));
	
	assign numer = NReg?IldSum1:IldSum2;
	assign denom = NReg?Hrs1Reg[30:0]:Hrs2Reg[30:0];

	always @(posedge CLK)	
	begin
		IldSum1 <= Sum1;
		IldSum2 <= Sum2;
	end
	
	always @(posedge CLK)
	begin
		if (!PumpDown)
		begin
			if (aSecond) //20000000分频
			begin
				Hrs1Reg <= Hrs1Reg + 1'b1;
				Hrs2Reg <= Hrs2Reg + 1'b1;
				MReg <= 26'd0;
			end
			else
				MReg <= MReg + 1'b1;
		end
	end
	
	always @(posedge CLK)
	begin
		Ild1Reg0 <= Ild1[30:15]; //整数部分
		Ild2Reg0 <= Ild2[30:15];
		if (PumpDown)
		begin
			Ild1Reg1 <= 16'd0;
			Ild2Reg1 <= 16'd0;
		end
		else begin
			Ild1Reg1 <= Ild1Reg0;
			Ild2Reg1 <= Ild2Reg0;
		end
	end
	
	always @(posedge CLK)
	begin
		if (!PumpDown)
			NReg <= ~NReg;
		if (NReg)
			Ildm1Reg1 <= AvgIld[31:0];
		else
			Ildm2Reg1 <= AvgIld[31:0];
	end
		
endmodule