pulse.v

FPGA verilog

module Pulse
	(
		CLK,
		Trigger,
		PulseOut
	);

	input	CLK;
	input	Trigger;
	output	PulseOut;
	
	reg		Q1,Q2;
	
	assign PulseOut =Q1&(~Q2);
	
	always @(negedge CLK)
	begin
		Q1 <= Trigger;
	end
	
	always @(negedge CLK)
	begin
		Q2 <= Q1;
	end
	
endmodule