alu.v

FPGA verilog

module Alu(
		AddrBus,
		ADData,
		REFLECT_K_Set,
		REFLECT_B_Set,
		PUMP_T_K3_Set,
		PUMP_T_K2_Set,
		PUMP_T_K1_Set,
		PUMP_T_K0_Set,
		MT_K_Set,
		MT_B_Set,
		CT_K3_Set,
		CT_K2_Set,
		CT_K1_Set,
		CT_K0_Set,
		ILD_K_Set,
		ILD_B_Set,
		ITC_K_Set,
		AD_VREF_K_Set,
		PUMP_PWR_K_Set,
		Result);

	`include "parameter.v"
	
	input	[12:0]			AddrBus;
	input	[11:0]			ADData;
	input 	[31:0]			REFLECT_K_Set,
							REFLECT_B_Set,
							PUMP_T_K3_Set,
							PUMP_T_K2_Set,
							PUMP_T_K1_Set,
							PUMP_T_K0_Set,
							MT_K_Set,
							MT_B_Set,
							CT_K3_Set,
							CT_K2_Set,
							CT_K1_Set,
							CT_K0_Set,
							ILD_K_Set,
							ILD_B_Set,
							ITC_K_Set,
							AD_VREF_K_Set,
							PUMP_PWR_K_Set;
				
output	[31:0] 	Result;

reg		[31:0] 	Result;

reg		[31:0]	K0,K1,K2,K3;

wire	[31:0] 	Stage1Result,
			   	Stage2Result,
			   	Stage3Result;
			
wire	[63:0] 	wire1,
			   	wire2,
			   	wire3;
wire	[31:0] 	result1,
			   	result2,
			   	result3;
wire	[31:0] 	X;

wire			TempCalc;

wire	[31:0]	TecSubResult;
reg		[31:0]	Stage2Inputa,Stage2Inputb,Stage3Input;

assign 	TempCalc = (AddrBus==CT_AD)|(AddrBus==PUMP_TMP_AD);

assign 	X = (TempCalc)?{20'h00,ADData}:{5'h00,ADData,15'h0000};

assign  result1 = (TempCalc)?wire1[31:0]:wire1[46:15];
assign  result2 = (TempCalc)?wire2[31:0]:wire2[46:15];
assign  result3 = (TempCalc)?wire3[61:30]:wire3[46:15];

/* X为IQ15,计算温度时K1,K2,K3为IQ30,K0为IQ15,其他计算均为IQ15 */

/* 第一级乘,*/
lpm_mult2	Stage1Mult(.dataa(K3),.datab(X),.result(wire1));
/* 第一级加*/
lpm_add0	Stage1Add(.dataa(result1),.datab(K2),.result(Stage1Result));//结果与输入数同点

/* 第二级乘*/
lpm_mult2	Stage2Mult(.dataa(Stage2Inputa),.datab(Stage2Inputb),.result(wire2));
/* 第二级加*/
lpm_add0	Stage2Add(.dataa(result2),.datab(K1),.result(Stage2Result));//结果与输入数同点

/* 第三级乘*/
lpm_mult2	Stage3Mult(.dataa(Stage2Result),.datab(Stage3Input),.result(wire3));
/* 第三级加*/
lpm_add0	Stage3Add(.dataa(result3),.datab(K0),.result(Stage3Result));//第3级加只有温度计算使用，所以将wire3转换为Q15

lpm_sub0 TecSub(.dataa(32'd49152000),//1500
				.datab(result1),
				.result(TecSubResult));
				
always @(AddrBus or 
		X or
		TecSubResult or 
		Stage1Result or
		REFLECT_K_Set or 
		REFLECT_B_Set or 
		PUMP_T_K3_Set or 
		PUMP_T_K2_Set or 
		PUMP_T_K1_Set or 
		PUMP_T_K0_Set or 
		MT_K_Set or 
		MT_B_Set or 
		CT_K3_Set or 
		CT_K2_Set or 
		CT_K1_Set or 
		CT_K0_Set or 
		ILD_K_Set or 
		ILD_B_Set or 
		ITC_K_Set or 
		AD_VREF_K_Set or 
		PUMP_PWR_K_Set)
begin

	case (AddrBus)
		PUMP_ILD_AD:
			begin
				Stage2Inputa = Stage1Result;
				Stage2Inputb = ILD_K_Set;
				Stage3Input = 0;
				K3 = AD_VREF_K_Set;
				K2 = 0;
				K1 = ILD_B_Set;
				K0 = 0;
			end
		PUMP_ITC_AD:
			begin
				Stage2Inputa = TecSubResult;
				Stage2Inputb = 32'd131072;//4;
				Stage3Input = ITC_K_Set;
				K3 = AD_VREF_K_Set;
				K2 = 0;
				K1 = 0;
				K0 = 0;
			end
		PUMP_PWR_AD:
			begin
				Stage2Inputa = Stage1Result;
				Stage2Inputb = ILD_K_Set;
				Stage3Input = PUMP_PWR_K_Set;		
				K3 = AD_VREF_K_Set;
				K2 = 0;
				K1 = ILD_B_Set;
				K0 = 0;
			end
		PUMP_TMP_AD:
			begin
				Stage2Inputa = Stage1Result;
				Stage2Inputb = X;
				Stage3Input = X;
				K3 = PUMP_T_K3_Set;
				K2 = PUMP_T_K2_Set;
				K1 = PUMP_T_K1_Set;
				K0 = PUMP_T_K0_Set;
			end
		MT_AD:
			begin
				Stage2Inputa = Stage1Result;
				Stage2Inputb = MT_K_Set;
				Stage3Input = 0;	
				K3 = AD_VREF_K_Set;
				K2 = 0;
				K1 = MT_B_Set;
				K0 = 0;
			end
		CT_AD:
			begin
				Stage2Inputa = Stage1Result;
				Stage2Inputb = X;
				Stage3Input = X;		
				K3 = CT_K3_Set;
				K2 = CT_K2_Set;
				K1 = CT_K1_Set;
				K0 = CT_K0_Set;
			end
		REFLECT_AD:
			begin
				Stage2Inputa = 0;
				Stage2Inputb = 0;
				Stage3Input = 0;	
				K3 = REFLECT_K_Set;
				K2 = REFLECT_B_Set;
				K1 = 0;
				K0 = 0;
			end
		default:
			begin
				Stage2Inputa = 0;
				Stage2Inputb = 0;
				Stage3Input = 0;	
				K3 = 0;
				K2 = 0;
				K1 = 0;
				K0 = 0;
			end
	endcase
end

always @(AddrBus or Stage1Result or Stage2Result or result3 or Stage3Result)//选择输出结果
begin
	case (AddrBus)
		REFLECT_AD:		Result = Stage1Result;
		MT_AD,
		PUMP_ILD_AD:	Result = Stage2Result;
		
		PUMP_ITC_AD,	
		PUMP_PWR_AD:	Result = result3;
			
		PUMP_TMP_AD,
		CT_AD:			Result = Stage3Result;
		default:		Result = 32'h00000000;
	endcase	
end

endmodule