losalarmmonitor.v

FPGA verilog

module LOSAlarmMonitor
	(
		EN,
		SYS_CLK,
		Param,
		Debounce_Time_Set,
		THR_Set,
		HYS_Set,
		T_AlarmOutput,
		Alarm_Output
	);
	
	input 			EN;
	input 			SYS_CLK;
	input	[31:0]	Param,
					THR_Set,
					HYS_Set;
	input	[31:0]	Debounce_Time_Set;
	output 			Alarm_Output;
	output			T_AlarmOutput;
	
	reg		[31:0]	InputParam;
	
	reg 			AlarmReg;
	reg 			AlarmSamp;
	wire			Alarm;
	
	reg		[31:0]	Activation_Time;
	
	
	function LTAlarm;
	input[31:0] Thr,
				Hys,
				Param;
	input		cAlarm;
	integer		iThr,
				iHys,
				iParam;
	
	reg 		AlarmTmp;
		begin
			iParam = Param;
			iThr = Thr;
			iHys = Hys;
			LTAlarm = cAlarm;
			AlarmTmp = iParam<iThr;
			if (cAlarm^AlarmTmp)
			begin
				if (cAlarm)
				begin
					if ((iParam-iHys)>iThr)
						LTAlarm = 1'b0;
				end
				else
					LTAlarm = 1'b1;
			end
		end
	endfunction

	assign Alarm = LTAlarm(THR_Set,HYS_Set,InputParam,AlarmReg);
	assign Alarm_Output = AlarmReg;
	assign T_AlarmOutput = AlarmSamp;
	
	always @(posedge SYS_CLK) 
	begin
		InputParam <= Param;
	end
	
	always @(posedge SYS_CLK) 
	begin
		AlarmSamp <= Alarm;
	end
	
	always @(posedge SYS_CLK)
	begin
		if (EN)
		begin
			if (AlarmReg^AlarmSamp)
			begin
				if (AlarmSamp)
				begin
					if (Activation_Time>=32'd10)
					begin
						AlarmReg <= 1'b1;
						Activation_Time <= 32'h0000;
					end
					else
						Activation_Time <= Activation_Time + 1'b1;
				end
				else begin
					if (Activation_Time>=Debounce_Time_Set)
					begin
						AlarmReg <= 1'b0;
						Activation_Time <=32'h0000;
					end
					else
						Activation_Time <= Activation_Time + 1'b1;
				end
			end
			else
				Activation_Time <= 32'h0000;
		end
		else begin
			AlarmReg <= 1'b0;
			Activation_Time <= 32'h0000;
		end
	end
	
endmodule