ltgt1alarmmonitor.v

FPGA verilog

module LTGT1AlarmMonitor
	(
		EN,
		SYS_CLK,
		Ref,
		Param,
		Debounce_Time_Set,
		THR_Set,
		HYS_Set,
		Alarm_Output
	);
	
	input 			EN;
	input 			SYS_CLK;
	input	[31:0]	Ref;
	input	[31:0]	Param,
					THR_Set,
					HYS_Set;
	input	[31:0]	Debounce_Time_Set;
	output 			Alarm_Output;
	
	reg 			AlarmReg;
	reg				AlarmSamp;
	wire			Alarm;
	
	reg		[31:0]	ParamReg;
	reg		[31:0]	Activation_Time;
	
	function GT_LT0Alarm;
	input[31:0] Thr_H,
				Hys_H,
				Thr_L,
				Hys_L,
				Param;
	input		cAlarm;
				
	integer 	iThr_H,
				iHys_H,
				iThr_L,
				iHys_L,
				iParam;
				
	reg 		AlarmTmp;
		begin
			iParam = Param;
			iThr_H = Thr_H;
			iHys_H = Hys_H;
			iThr_L = Thr_L;
			iHys_L = Hys_L;
			GT_LT0Alarm = cAlarm;
			AlarmTmp = (iParam>iThr_H)||(iParam<iThr_L);
			if (cAlarm^AlarmTmp)
			begin
				if (cAlarm)
				begin
					if (((iParam+iHys_H)<iThr_H)&&((iParam-iHys_L)>iThr_L))
						GT_LT0Alarm = 1'b0;
				end
				else
					GT_LT0Alarm = 1'b1;
			end
		end
	endfunction

	
	function GT_LT1Alarm;
	input[31:0] Ref,
				Thr,
				Hys,
				Param;
	input		cAlarm;
				
	integer	 	iThr_H,
				iHys,
				iThr_L,
				iTmpa,
				iTmpb;
		begin
			iTmpa = Ref;
			iTmpb = Thr;
			iThr_H = iTmpa+iTmpb;
			iThr_L = iTmpa-iTmpb;
			iHys = Hys;
			GT_LT1Alarm = GT_LT0Alarm(iThr_H,iHys,iThr_L,iHys,Param,cAlarm);
		end
	endfunction

	assign Alarm = GT_LT1Alarm(Ref,THR_Set,HYS_Set,ParamReg,AlarmReg);
	assign Alarm_Output = AlarmReg;

	always @(negedge SYS_CLK)
	begin
		ParamReg <= Param;
	end
	
	always @(posedge SYS_CLK)
	begin
		AlarmSamp <= Alarm;
	end
	
	always @(posedge SYS_CLK)
	begin
		if (EN)
		begin
			if (AlarmReg^AlarmSamp)
			begin
				if (AlarmSamp)
				begin
					if (Activation_Time>=32'd10)
					begin
						AlarmReg <= 1'b1;
						Activation_Time <= 32'h0000;
					end
					else
						Activation_Time <= Activation_Time + 1'b1;
				end
				else begin
					if (Activation_Time>=Debounce_Time_Set)
					begin
						AlarmReg <= 1'b0;
						Activation_Time <= 32'h0000;
					end
					else
						Activation_Time <= Activation_Time + 1'b1;
				end
			end
			else
				Activation_Time <= 32'h0000;
		end
		else begin
			Activation_Time <= 32'h0000;
		end
	end
	
endmodule