modectrlnew.v

FPGA verilog

module ModeCtrl(
		CLK,
		EN,
		OP_MODE_Set,
		LOSMODE_Set,
		AUTO_MUTE_Set,
		APC_KP_Set,
		APC_KI_Set,
		PLIM_Set,
		GLIM_Set,
		AGC_KP_Set,
		AGC_KI_Set,
		OFG_Set,
		TARGET_GAIN_Set,
		TARGET_PWR_Set,
		EYESAFE_PWR_Set,
		MUTEON_Set,
		PUMPON_Set,	
		Pump_Protect_Alarm,
		Ramp,
		Input_LOS_Alarm,
		Reflection_Alarm,
		Amplifier_Disable_Input,
		Output_Mute_Input,
		OutputPwrAsmW,
		InputPwrAsmW,
		Gain,
		A,
		B,
		POutsig,
		FeedForwardData,
		OpModeOut,
		PumpDown,
		RampStart,
		Mst,
		Pump_DacData
);
	`include "parameter.v"
	input	CLK;
	input	EN;
	input	Amplifier_Disable_Input;
	input	Output_Mute_Input;
	input	Pump_Protect_Alarm;
	input	Ramp;
	input	Input_LOS_Alarm;
	input	Reflection_Alarm;
	input	AUTO_MUTE_Set;
	input	MUTEON_Set;
	input	PUMPON_Set;	
	input	[1:0]	LOSMODE_Set;
	input	[2:0]	OP_MODE_Set;
	input	[31:0]	APC_KP_Set,
					APC_KI_Set,
					PLIM_Set,
					GLIM_Set,
					AGC_KP_Set,
					AGC_KI_Set,
					OFG_Set,
					A,
					B,
					TARGET_GAIN_Set,
					TARGET_PWR_Set,
					EYESAFE_PWR_Set;
	
	input	[31:0] 	Gain,
					OutputPwrAsmW,
					InputPwrAsmW,
					POutsig;
	input	[11:0]	FeedForwardData;
					
	output	[2:0] 	OpModeOut;
	output			PumpDown;
	output			RampStart;
	output	[2:0]	Mst;
	output	[11:0] 	Pump_DacData;
			
	reg				PumpDown;
	reg				RampStart;
	reg		[31:0] 	Ki;
	reg		[31:0] 	Kp;
	reg		[31:0] 	NextPoint;
	reg		[31:0] 	Target;
	
	wire			FeedForwardEN;
	wire			Amplifier_Disable_Input_Single;
	wire			Output_Mute_Input_Single;
	
	wire	Lim_Signal,Dis_Signal,Es_Signal;	
	
	reg	[2:0]	OpModeSet_Q0,OpModeSet;
	
	reg [2:0]	OpMode,NextMode,OrgOpMode;

	wire	[55:0]	MaxPSigSignal;
	wire	[31:0]	POutSignal;
	reg		[31:0]	POutSignalReg;
	reg		[31:0]	MaxPSigSignalReg;

	wire	[31:0]	PwrSet;

	reg	   POutOver,GainOver;
	reg    POutOverReg,GainOverReg;

	wire		OverFlag,Idled,isAGCMode,isAPCMode;
	
	assign	OpModeOut = OpMode;

	assign Idled = Input_LOS_Alarm&(LOSMODE_Set==LM_AGC_IDLE)&(OpModeSet==AGC_MODE);
	
	assign Lim_Signal = POutOverReg|GainOverReg;
	assign Dis_Signal = (OpMode==PD_MODE)|Es_Signal;
	assign Es_Signal =  (OpMode==APR_MODE);
	assign Mst = {Dis_Signal,Es_Signal,Lim_Signal};
	
	assign  FeedForwardEN  = (isAGCMode)&(~POutOverReg);
	assign 	isAGCMode = OrgOpMode==AGC_MODE;
	assign  isAPCMode = OrgOpMode==APC_MODE;

	InputFilter Amplifier_Disable_KeyFilter(
				.CLK(CLK),
				.KeyInput(Amplifier_Disable_Input),
				.KeyOutput(Amplifier_Disable_Input_Single));

	InputFilter Output_Mute_KeyFilter(
				.CLK(CLK),
				.KeyInput(Output_Mute_Input),
				.KeyOutput(Output_Mute_Input_Single));

	PIDTune	modePIDTune(
			.EN(EN&(!Idled)),
			.Ramp(Ramp),
			.FeedForwardEN(FeedForwardEN),
			.FeedForwardData(FeedForwardData),
			.CLK(CLK),
			.Ki(Ki),
			.Kp(Kp),
			.NextPoint(NextPoint),
			.Target(Target),
			.PIDResult(Pump_DacData));

	wire 	[23:0]	Pin_A;
	wire	[55:0]	Gain_Pin_A;
	
	lpm_add_signed_24	b2v_add2(.dataa(InputPwrAsmW[23:0]),
						.datab(A[23:0]),
						.result(Pin_A));					
    lpm_mult_unsigned_24x32_hard	b2v_inst7(.dataa(Pin_A),
					.datab(TARGET_GAIN_Set),
					.result(Gain_Pin_A)); 
	lpm_sub_signed_32	b2v_sub1(.dataa(Gain_Pin_A[46:15]),
						.datab(B),
						.result(POutSignal)); //总功率					

    lpm_mult_unsigned_24x32_hard	b2v_inst8(.dataa(InputPwrAsmW[23:0]),
					.datab(GLIM_Set),
					.result(MaxPSigSignal)); 

	assign	PwrSet = isAGCMode?POutSignalReg:(isAPCMode?TARGET_PWR_Set:EYESAFE_PWR_Set);
	assign  OverFlag = {5'b00000,PwrSet[31:5]}>MaxPSigSignalReg;
	
	always @(GLIM_Set or TARGET_GAIN_Set or PwrSet or OverFlag or isAGCMode)
	begin
		if ((TARGET_GAIN_Set>GLIM_Set)&&isAGCMode||OverFlag&&(!isAGCMode))
			GainOver = 1'b1;
		else
			GainOver = 1'b0;
	end

	always @(PLIM_Set or PwrSet)
	begin
		if (PwrSet>PLIM_Set)
			POutOver = 1'b1;
		else
			POutOver = 1'b0;
	end

	always @(posedge CLK)
	begin
		POutSignalReg <= POutSignal;
		MaxPSigSignalReg <= MaxPSigSignal[51:20];
	  	GainOverReg <= GainOver;
	    POutOverReg <= POutOver;
	end
	

	always @(posedge CLK)
	begin
		OpModeSet_Q0 <= OP_MODE_Set;
		OpModeSet <= OpModeSet_Q0;
	end
	
	always @(posedge CLK)
	begin
		if (NextMode==PD_MODE)
			PumpDown = 1'b1; 
		else
			PumpDown = 1'b0; 
	end
	
	always @(posedge CLK)
	begin
		if (OpMode == NextMode)
			RampStart <=1'b0;
		else begin
			OpMode <= NextMode;
			if (NextMode!=ACC_MODE)
				OrgOpMode <= NextMode;
			
			RampStart <= 1'b1;
		end
	end
	
    always @(Amplifier_Disable_Input_Single or 
			Output_Mute_Input_Single or 
			PUMPON_Set or 
			Input_LOS_Alarm or 
			LOSMODE_Set or 
			Reflection_Alarm or 
			AUTO_MUTE_Set or 
			MUTEON_Set or 
			OpModeSet or
			Pump_Protect_Alarm) 
	begin
		if (Amplifier_Disable_Input_Single||
			(!PUMPON_Set)||Pump_Protect_Alarm||
			(Input_LOS_Alarm&&((OpModeSet==AGC_MODE)?(LOSMODE_Set==LM_AGC_DIS):(LOSMODE_Set!=LM__NO_EFFECT))))
			NextMode <= PD_MODE;
		else if (Output_Mute_Input_Single||(Reflection_Alarm&&AUTO_MUTE_Set)||MUTEON_Set)
			NextMode <= APR_MODE;
		else
			NextMode <= OpModeSet;
	end

	
	always @(POutOverReg or
			GainOverReg or
			APC_KP_Set or 
			APC_KI_Set or
			PLIM_Set or
			OutputPwrAsmW or
			OrgOpMode or
			AGC_KP_Set or
			AGC_KI_Set or
			TARGET_GAIN_Set or
			Gain or
			POutsig or
			TARGET_PWR_Set or
			EYESAFE_PWR_Set or 
			GLIM_Set or 
			MaxPSigSignalReg)
	begin
		/*if (POutOverReg&&(({5'b00000,PLIM_Set[31:5]}<=MaxPSigSignalReg)))
		begin
			Kp = APC_KP_Set;
			Ki = APC_KI_Set;
			Target = PLIM_Set;
			NextPoint = OutputPwrAsmW;
		end
		else if (GainOverReg)
		begin
			Kp = AGC_KP_Set;
			Ki = AGC_KI_Set;
			Target = GLIM_Set;
			NextPoint = Gain;
		end
		else*/
		begin
			case (OrgOpMode)
				AGC_MODE:
					begin
						Kp = AGC_KP_Set;
						Ki = AGC_KI_Set;
						Target = TARGET_GAIN_Set;
						NextPoint = Gain;
					end
				APC_MODE:
					begin
						Kp = APC_KP_Set;
						Ki = APC_KI_Set;
						Target = TARGET_PWR_Set;
						NextPoint = POutsig;
					end
				APR_MODE:
					begin
						Kp = APC_KP_Set;
						Ki = APC_KI_Set;
						Target = EYESAFE_PWR_Set;
						NextPoint = OutputPwrAsmW;
					end	
				default:
					begin
						Kp = 0;
						Ki = 0;
						Target = 0;
						NextPoint = 0;
					end
			endcase
		end
	end
	
endmodule