voa.v

FPGA verilog

module VOA
(
	//Input
	EN,
	CLK,
	VOA_INPUT_K_Set,
	VOA_INPUT_B_Set,
	VOA_OUTPUT_K_Set,
	VOA_OUTPUT_B_Set,
	VOAInputAD,
	VOAOutputAD,
	VOA_Target,
	VOA_KP_Set,
	VOA_KI_Set, 
	//Output	
	VOAInputPwr,
	VOAOutputPwr,
	VOAAtt,
	VOA_DacOutput
);
	input 			CLK;
	input			EN;
	input 	[31:0]	VOA_INPUT_K_Set,
					VOA_INPUT_B_Set,
					VOA_OUTPUT_K_Set,
					VOA_OUTPUT_B_Set,
					VOA_KP_Set,
					VOA_KI_Set, 
					VOA_Target;
	input	[11:0]	VOAInputAD,
					VOAOutputAD;
	output 	[11:0] 	VOA_DacOutput;
	
	
	reg		[11:0]	InputADReg,
					OutputADReg;
	reg		[24:0]	InputPwrReg,
					OutputPwrReg;
					
	reg		[31:0] SumError;

	wire	[48:0] Err_P;
	wire	[48:0] Err_I;

	wire 	[31:0] Error,Error_Single;

	reg		[31:0]	mInputa,mInputb;
	wire	[48:]	mResult;
	
	wire			Update;
	reg		[8:0]	Counter;
	
	
	lpm_mult1	b2v_inst2(.dataa(mInput),
					.datab(mInputb),
					.result(mResult));
	
	assign Update = Counter[8]==1'b1;
	
	
	always @(Counter)
	begin
		case (Counter)
			1'b1:
				mInput = VOAInputAD;
				
		endcase
	end
	
	always @(posedge CLK)
	begin
		if (Update)
		begin
		end
		else begin
			case (Counter[)
				1'b1:
					
				InputADReg <= VOAInputAD;
				OutputADReg <= VOAOutputAD;
		end
	end
	
	
endmodule