adcalarmmonitor.v

FPGA verilog

module ADCAlarmMonitor
	(
		EN,
		CLK,
		InputPwr, 
		POutsig,
		Gain, 
		OpMode, 
		LOS_THR_Set,
		LOS_HYS_Set,
		LOP_THR_HI_Set,
		LOP_THR_LO_Set,
		LOP_HYS_HI_Set,
		LOP_HYS_LO_Set,
		Debounce_Time_Set,
		Input_LOS_Alarm_Output,
		Output_LOP_Alarm_Output
	);
	
	`include "parameter.v"
	
	input				EN;
	input				CLK;
	input	[1:0]		OpMode;
	input 	[31:0]		Debounce_Time_Set;
	input 	[31:0] 		InputPwr;
	input 	[31:0] 		POutsig,
						Gain,
						LOS_THR_Set,
						LOS_HYS_Set,
						LOP_THR_HI_Set,
						LOP_THR_LO_Set,
						LOP_HYS_HI_Set,
						LOP_HYS_LO_Set;
							
	output				Input_LOS_Alarm_Output;
	output				Output_LOP_Alarm_Output;
	
	wire	[31:0]		LOP_Param;
	wire				AGCCtrl;
	wire				LopAlarmEn;
	
	
	assign AGCCtrl = OpMode==AGC_MODE;
	assign LOP_Param = AGCCtrl?Gain:POutsig;
	assign LopAlarmEn = (AGCCtrl|(OpMode==APC_MODE));
	
	LTAlarmMonitor LOSLTAlarmMonitor(
				.EN(EN),
				.SYS_CLK(CLK),
				.Param(InputPwr),
				.Debounce_Time_Set(Debounce_Time_Set),
				.THR_Set(LOS_THR_Set),
				.HYS_Set(LOS_HYS_Set),
				.Alarm_Output(Input_LOS_Alarm_Output)
			);
			
	DOPAlarmMonitor LOPAlarmMonitor(
				.EN(EN),
				.AlarmEN(LopAlarmEn),
				.SYS_CLK(CLK),
				.Param(LOP_Param),
				.Debounce_Time_Set(Debounce_Time_Set),
				.LOP_THR_HI_Set(LOP_THR_HI_Set),
				.LOP_THR_LO_Set(LOP_THR_LO_Set),
				.LOP_HYS_HI_Set(LOP_HYS_HI_Set),
				.LOP_HYS_LO_Set(LOP_HYS_LO_Set),
				.Alarm_Output(Output_LOP_Alarm_Output)
			);
endmodule