pump.v

FPGA verilog

module Pump
	(
		CLK,
		PumpDown,
		Ild,
		Hrs,
		Ildm
	);

	input			CLK;
	input			PumpDown;
	input	[31:0]	Ild;
	output	[31:0]	Hrs;
	output	[31:0]	Ildm;
	
	reg		[25:0]	MReg;
	
	reg		[31:0]	HrsReg;

	reg		[15:0]	IldReg0,IldReg1;

	reg		[31:0]	IldmReg;
	
	wire	[30:0]	denom;
	wire	[39:0]	numer;
	wire	[39:0]	AvgIld;
	reg		[39:0]	IldSum;

	wire	[39:0]	Sum;
	
	wire	aSecond,AccEN;
	
	assign	aSecond = MReg==26'd19999999;
	assign  AccEN = aSecond&(~PumpDown);
	
	assign  Hrs = HrsReg;
	assign  Ildm = IldmReg;

	lpm_acc_i16_o40 IldAcc(
				.clock(CLK),
				.clken(AccEN),
				.data(IldReg1),
				.result(Sum));

	lpm_divide_ildm Ildmdiv(
				.clock(CLK),
				.denom(denom),
				.numer(numer),
				.quotient(AvgIld));
	
	assign numer =IldSum;
	assign denom = HrsReg[30:0];

	always @(posedge CLK)	
	begin
		IldSum <= Sum;
	end
	
	always @(posedge CLK)
	begin
		if (!PumpDown)
		begin
			if (aSecond) //20000000分频
			begin
				HrsReg <= HrsReg + 1'b1;
				MReg <= 26'd0;
			end
			else
				MReg <= MReg + 1'b1;
		end
	end
	
	always @(posedge CLK)
	begin
		IldReg0 <= Ild[30:15]; //整数部分
		if (PumpDown)
		begin
			IldReg1 <= 16'd0;
		end
		else begin
			IldReg1 <= IldReg0;
		end
	end
	
	always @(posedge CLK)
	begin
		IldmReg <= AvgIld[31:0];
	end
		
endmodule