voactrl.v

FPGA verilog

module VOACtrl
(
	EN,
	CLK,
	Ramp,
	OpMode,
	VOA_SET_Set,
	VOATarget,
	VOAAtt,
	VOA_KP_Set,
	VOA_KI_Set, 
	VOA_DacData
);
	input 			CLK;
	input			EN;
	input			Ramp;
	input	[1:0]	OpMode;
	input	[31:0]	VOAAtt;
	input 	[31:0] 	VOA_KP_Set,
					VOA_KI_Set, 
					VOA_SET_Set,
					VOATarget;
	output 	[11:0] 	VOA_DacData;
	
	wire	[31:0]	Target;
	wire			AGCCtrl;
	
	`include "parameter.v"
	
	assign	AGCCtrl = OpMode==AGC_MODE;
	
	assign Target = AGCCtrl?VOATarget:VOA_SET_Set;
	
	VOAPIDTune	b2v_inst2(
			.EN(EN),
			.Ramp(Ramp),
			.CLK(CLK),
			.Ki(VOA_KI_Set),
			.Kp(VOA_KP_Set),
			.NextPoint(VOAAtt),
			.Target(Target),
			.PIDResult(VOA_DacData));
	
endmodule