dacbak23.v

FPGA verilog

module DAC
(
	DAC_CLK,
	VOA_CLK,
	OpMode,
	CURR_SET_Set,
	VOA_DAC_SetReg,
	Pump_DacData, 
	VOA_DacData, 
	Pump_DacOut, 
	VOA_DacOut
);
    `include "parameter.v"

	input 			DAC_CLK;
	input 			VOA_CLK;
	input	[2:0]	OpMode;
	input	[11:0]	CURR_SET_Set;
	input 	[11:0] 	Pump_DacData;
	input 	[11:0] 	VOA_DacData;
	input 	[11:0]	VOA_DAC_SetReg;
	output 	[11:0] 	Pump_DacOut;
	output 	[11:0] 	VOA_DacOut;


	reg 	[11:0] 	Pump_DacOut;
	reg 	[11:0] 	VOA_DacOut;
	
	reg		[11:0]	Q0,Q1;
	
	wire			ACCCtrl;
	wire			PumpDown;
	
	assign 	ACCCtrl = OpMode==ACC_MODE;
	assign 	PumpDown = OpMode==PD_MODE;
	
	always @(negedge DAC_CLK)
	begin
		Q0 <= Pump_DacData;
	end

	always @(negedge VOA_CLK)
	begin
		Q1 <= VOA_DacData;
	end

	always @(negedge DAC_CLK)
	begin
		if (ACCCtrl)
			Pump_DacOut <= CURR_SET_Set;
		else if (PumpDown)
			Pump_DacOut <= 12'd0;
		else if (OpMode!=IDLE_MODE)
			Pump_DacOut <= Q0;
	end

	always @(negedge VOA_CLK)
	begin
		if (ACCCtrl)
			VOA_DacOut <= VOA_DAC_SetReg;
		else if (PumpDown)
			VOA_DacOut <= 12'd4095;
		else if (OpMode==AGC_MODE)
			VOA_DacOut <= Q1;
		else
			VOA_DacOut <= 12'd000;
	end
endmodule