adc.v

FPGA verilog

module ADC
	(
		//Input
		CLK,
		PIN_K_Set,
		PIN_B_Set,		
		POUT_K_Set,
		POUT_B_Set,
		VOA_INPUT_K_Set,
		VOA_INPUT_B_Set,
		VOA_OUTPUT_K_Set,
		VOA_OUTPUT_B_Set,
		RFL_K_Set,
		RFL_B_Set,
		InputPwrAD,
		VOAInputAD,
		VOAOutputAD,
		OutputPwrAD,
		RFLAD,
		//Output
		VOAInputPwr,
		VOAOutputPwr,
		OutputPwr,
		InputPwr,
		RFLPwr,
		VOAAtt
	);
	
	input			CLK;
	input	[31:0]	PIN_K_Set;
	input	[31:0]	PIN_B_Set;
	input	[31:0]	POUT_K_Set;
	input	[31:0]	POUT_B_Set;
	input	[31:0]	VOA_INPUT_K_Set;
	input	[31:0]	VOA_INPUT_B_Set;
	input	[31:0]	VOA_OUTPUT_K_Set;
	input	[31:0]	VOA_OUTPUT_B_Set;
	input	[31:0]	RFL_K_Set;
	input	[31:0]	RFL_B_Set;
	input	[11:0] 	InputPwrAD;	
	input	[11:0] 	OutputPwrAD;	
	input	[11:0] 	VOAInputAD;
	input	[11:0] 	VOAOutputAD;
	input	[11:0] 	RFLAD;
	
	output	[31:0]	VOAInputPwr;
	output	[31:0]	VOAOutputPwr;
	output	[31:0]	OutputPwr;
	output	[31:0]	InputPwr;
	output	[31:0]	RFLPwr;
	output	[31:0]	VOAAtt;

	reg		[31:0]	VOAAtt;
	reg		[31:0]	OutputPwr;
	reg		[31:0]	InputPwr;
	reg		[31:0]	RFLPwr;
	
	wire	[31:0]	Result1,Result2,Result3,Result4,Result5;	
	wire	[31:0]	Att;
	reg		[31:0]	VOAInputPwr0;
	reg		[31:0]	VOAOutputPwr0;
	
	integer 		iAtt,ia;
	reg				VoaError;

	wire	[11:0]	InputAD_Filter,
					OutputAD_Filter,
					VoaInAD_Filter,
					VoaOutAD_Filter,
					RFLAD_Filter;

	ADCCh	InputAdFilter(.CLK(CLK),.InputAD(InputPwrAD),.OutputAD(InputAD_Filter));
	ADCCh	OutputAdFilter(.CLK(CLK),.InputAD(OutputPwrAD),.OutputAD(OutputAD_Filter));
							
	ADCCh	VOAInputAdFilter(.CLK(CLK),.InputAD(VOAInputAD),.OutputAD(VoaInAD_Filter));
	ADCCh	VOAOutputAdFilter(.CLK(CLK),.InputAD(VOAOutputAD),.OutputAD(VoaOutAD_Filter));

	ADCCh	RFLAdFilter(.CLK(CLK),.InputAD(RFLAD),.OutputAD(RFLAD_Filter));

	K_BCalculator InputCalculator(.K(PIN_K_Set),
							.B(PIN_B_Set),
							.X(InputAD_Filter),
							.result(Result1));


	K_BCalculator OutputCalculator(.K(POUT_K_Set),
							.B(POUT_B_Set),
							.X(OutputAD_Filter),
							.result(Result2));

	K_BCalculator VoaInCalculator(.K(VOA_INPUT_K_Set),
							.B(VOA_INPUT_B_Set),
							.X(VoaInAD_Filter),
							.result(Result3));

	K_BCalculator VoaOutCalculator(.K(VOA_OUTPUT_K_Set),
							.B(VOA_OUTPUT_B_Set),
							.X(VoaOutAD_Filter),
							.result(Result4));
	
	K_BCalculator RFLCalculator(.K(RFL_K_Set),
							.B(RFL_B_Set),
							.X(RFLAD_Filter),
							.result(Result5));
	
	lpm_sub_signed_32	VOA_Sub(
					.dataa(VOAInputPwr0),
					.datab(VOAOutputPwr0),
					.result(Att));
	
	assign VOAInputPwr = VOAInputPwr0;
	assign VOAOutputPwr = VOAOutputPwr0;
	
	always @(posedge CLK)
	begin
		InputPwr <= Result1;
		OutputPwr <= Result2;
		VOAInputPwr0 <= Result3;
		VOAOutputPwr0 <= Result4;
		RFLPwr <= Result5;
	end
	
	always @(Att)
	begin
		iAtt = Att;
		ia = 327;
		if (iAtt<ia)
			VoaError = 1'b1;
		else
			VoaError = 1'b0;
	end
	
	always @(posedge CLK)
	begin
		if (VoaError)
			VOAAtt <= 327;
		else
			VOAAtt <= Att;
	end
	
endmodule