compare3_tb.vcd

来自「PacoBlaze is a from-scratch synthesizabl」· VCD 代码 · 共 2,065 行 · 第 1/5 页

$date
    Tue Mar 21 00:12:42 2006
$end
$version
    GPLCVER_2.11a of 07/05/05
$end
$timescale
    1 ps
$end
$scope module compare3_tb $end
$var wire      10 !    ad_0 [9:0] $end
$var wire      10 "    ad_1 [9:0] $end
$var reg       1 #    clk $end
$var wire      18 $    di_0 [17:0] $end
$var wire      18 %    di_1 [17:0] $end
$var integer      32 &    i [31:0] $end
$var wire       1 '    ia_0 $end
$var wire       1 (    ia_1 $end
$var reg       1 )    ir $end
$var wire       8 *    pa_0 [7:0] $end
$var wire       8 +    pa_1 [7:0] $end
$var wire       8 ,    pi_0 [7:0] $end
$var wire       8 -    pi_1 [7:0] $end
$var wire       8 .    po_0 [7:0] $end
$var wire       8 /    po_1 [7:0] $end
$var wire       1 0    rd_0 $end
$var wire       1 1    rd_1 $end
$var reg       1 2    rst $end
$var wire       1 3    wr_0 $end
$var wire       1 4    wr_1 $end
$scope module rom_0 $end
$var wire      10 5    ad [9:0] $end
$var wire       1 6    clk $end
$var wire      18 7    di [17:0] $end
$var reg      18 8    do [17:0] $end
$var wire       1 9    en $end
$var wire       1 :    rst $end
$var wire       1 ;    we $end
$upscope $end
$scope module dut_0 $end
$var wire      10 <    address [9:0] $end
$var wire       1 =    alu_carry_out $end
$var wire       8 >    alu_operand_a [7:0] $end
$var wire       8 ?    alu_operand_b [7:0] $end
$var wire       8 @    alu_result [7:0] $end
$var wire       1 A    alu_zero_out $end
$var reg       1 B    carry $end
$var reg       1 C    carry_saved $end
$var wire       1 D    clk $end
$var wire       1 E    conditional_match $end
$var wire      10 F    idu_code_address [9:0] $end
$var wire       2 G    idu_condition_flags [1:0] $end
$var wire       1 H    idu_conditional $end
$var wire     256 I    idu_debug_opcode [256:1] $end
$var wire       8 J    idu_implied_value [7:0] $end
$var wire       1 K    idu_interrupt_enable $end
$var wire       1 L    idu_operand_selection $end
$var wire       5 M    idu_operation [4:0] $end
$var wire       8 N    idu_port_address [7:0] $end
$var wire       6 O    idu_scratch_address [5:0] $end
$var wire       1 P    idu_shift_constant $end
$var wire       1 Q    idu_shift_direction $end
$var wire       3 R    idu_shift_operation [2:0] $end
$var wire       4 S    idu_x_address [3:0] $end
$var wire       4 T    idu_y_address [3:0] $end
$var wire       8 U    in_port [7:0] $end
$var wire      18 V    instruction [17:0] $end
$var wire       1 W    internal_reset $end
$var wire       1 X    interrupt $end
$var reg       1 Y    interrupt_ack $end
$var wire       1 Z    interrupt_assert $end
$var reg       1 [    interrupt_enable $end
$var reg       1 \    interrupt_latch $end
$var wire       1 ]    is_call $end
$var wire       1 ^    is_fetch $end
$var wire       1 _    is_input $end
$var wire       1 `    is_jump $end
$var wire       1 a    is_return $end
$var wire       1 b    is_returni $end
$var wire       8 c    out_port [7:0] $end
$var wire       8 d    port_id [7:0] $end
$var reg      10 e    program_counter [9:0] $end
$var wire      10 f    program_counter_next [9:0] $end
$var wire      10 g    program_counter_source [9:0] $end
$var reg       1 h    read_strobe $end
$var wire       8 i    register_x_data_in [7:0] $end
$var wire       8 j    register_x_data_out [7:0] $end
$var reg       1 k    register_x_write_enable $end
$var wire       8 l    register_y_data_out [7:0] $end
$var wire       1 m    reset $end
$var reg       2 n    reset_latch [1:0] $end
$var wire       6 o    scratch_address [5:0] $end
$var wire       8 p    scratch_data_out [7:0] $end
$var reg       1 q    scratch_write_enable $end
$var wire      10 r    stack_data_in [9:0] $end
$var wire      10 s    stack_data_out [9:0] $end
$var wire       1 t    stack_push_pop $end
$var wire       1 u    stack_update_enable $end
$var wire       1 v    stack_write_enable $end
$var reg       1 w    timing_control $end
$var reg       1 x    write_strobe $end
$var reg       1 y    zero $end
$var reg       1 z    zero_carry_write_enable $end
$var reg       1 {    zero_saved $end
$scope begin seq $end
$scope begin on_run $end
$upscope $end
$scope begin on_internal_reset $end
$upscope $end
$upscope $end
$scope begin on_reset $end
$upscope $end
$scope task execute $end
$var reg       5 |    operation [4:0] $end
$upscope $end
$scope module idu $end
$var wire      10 }    code_address [9:0] $end
$var wire       2 "!   condition_flags [1:0] $end
$var wire       1 ""   conditional $end
$var reg      16 "#   debug_conditional [16:1] $end
$var reg      56 "$   debug_interrupt [56:1] $end
$var reg     256 "%   debug_opcode [256:1] $end
$var reg      40 "&   debug_operand [40:1] $end
$var wire       8 "'   implied_value [7:0] $end
$var wire      18 "(   instruction [17:0] $end
$var wire       5 ")   instruction_0 [4:0] $end
$var wire       1 "*   interrupt_enable $end
$var wire       1 "+   operand_selection $end
$var reg       5 ",   operation [4:0] $end
$var wire       8 "-   port_address [7:0] $end
$var wire       6 ".   scratch_address [5:0] $end
$var wire       1 "/   shift_constant $end
$var wire       1 "0   shift_direction $end
$var wire       3 "1   shift_operation [2:0] $end
$var wire       4 "2   x_address [3:0] $end
$var wire       4 "3   y_address [3:0] $end
$scope function adrtohex $end
$var reg      18 "6   address [17:0] $end
$var reg      24 "7   adrtohex [24:1] $end
$upscope $end
$scope function numtohex $end
$var reg       4 "4   number [3:0] $end
$var reg       8 "5   numtohex [8:1] $end
$upscope $end
$upscope $end
$scope module alu $end
$var wire       8 "8   addsub_b [7:0] $end
$var wire       1 "9   addsub_carry $end
$var wire       9 ":   addsub_result [8:0] $end
$var wire       1 ";   carry_in $end
$var reg       1 "<   carry_out $end
$var wire       8 "=   operand_a [7:0] $end
$var wire       8 ">   operand_b [7:0] $end
$var wire       5 "?   operation [4:0] $end
$var reg       8 "@   result [7:0] $end
$var wire       1 "A   shift_bit $end
$var wire       1 "B   shift_constant $end
$var wire       1 "C   shift_direction $end
$var wire       3 "D   shift_operation [2:0] $end
$var wire       1 "E   zero_out $end
$scope begin on_alu $end
$upscope $end
$upscope $end
$scope module register $end
$var wire       1 "F   clk $end
$var wire       1 "G   reset $end
$var wire       4 "H   x_address [3:0] $end
$var wire       8 "I   x_data_in [7:0] $end
$var wire       8 "J   x_data_out [7:0] $end
$var wire       1 "K   x_write_enable $end
$var wire       4 "L   y_address [3:0] $end
$var wire       8 "M   y_data_out [7:0] $end
$upscope $end
$scope module stack $end
$var wire       1 "N   clk $end
$var wire      10 "O   data_in [9:0] $end
$var wire      10 "P   data_out [9:0] $end
$var reg       5 "Q   ptr [4:0] $end
$var wire       5 "R   ptr_1 [4:0] $end
$var wire       1 "S   push_pop $end
$var wire       1 "T   reset $end
$var wire       1 "U   update_enable $end
$var wire       1 "V   write_enable $end
$upscope $end
$scope module scratch $end
$var wire       6 "W   address [5:0] $end
$var wire       1 "X   clk $end
$var wire       8 "Y   data_in [7:0] $end
$var wire       8 "Z   data_out [7:0] $end
$var wire       1 "[   reset $end
$var wire       1 "\   write_enable $end
$upscope $end
$upscope $end
$scope module rom_1 $end
$var wire      10 "]   ad [9:0] $end
$var wire       1 "^   clk $end
$var wire      18 "_   di [17:0] $end
$var reg      18 "`   do [17:0] $end
$var wire       1 "a   en $end
$var wire       1 "b   rst $end
$var wire       1 "c   we $end
$upscope $end
$scope module dut_1 $end
$var wire      24 "d   aaa_decode [1:24] $end
$var wire       1 "e   active_interrupt $end
$var wire      10 "f   address [9:0] $end
$var wire       8 "g   alu_group [7:0] $end
$var wire       8 "h   alu_result [7:0] $end
$var wire       1 "i   arith_carry $end
$var wire       1 "j   arith_carry_in $end
$var wire       1 "k   arith_carry_out $end
$var wire       8 "l   arith_internal_carry [7:0] $end
$var wire       8 "m   arith_result [7:0] $end
$var wire       8 "n   arith_value [7:0] $end
$var wire       1 "o   call_type $end
$var wire       1 "p   carry_fast_route $end
$var wire       1 "q   carry_flag $end
$var wire       1 "r   clean_int $end
$var wire       1 "s   clk $end
$var wire       1 "t   condition_met $end
$var wire       1 "u   flag_enable $end
$var wire       1 "v   flag_type $end
$var wire       1 "w   flag_write $end
$var wire       8 "x   half_arith [7:0] $end
$var wire       5 "y   half_stack_address [4:0] $end
$var wire       1 "z   high_parity $end
$var wire       1 "{   high_shift_in $end
$var wire       1 "|   high_zero $end
$var wire       1 "}   high_zero_carry $end
$var wire       8 #!   in_port [7:0] $end
$var wire      10 #"   inc_pc_value [9:0] $end
$var wire      10 ##   inc_pc_vector [9:0] $end
$var wire       1 #$   input_fetch_type $end
$var wire       8 #%   input_group [7:0] $end
$var wire      18 #&   instruction [17:0] $end
$var wire       1 #'   int_enable $end
$var wire       1 #(   int_enable_value $end
$var wire       1 #)   int_pulse $end
$var wire       1 #*   int_update_enable $end
$var wire       1 #+   internal_reset $end
$var wire       1 #,   interrupt $end
$var wire       1 #-   interrupt_ack $end
$var wire       1 #.   interrupt_ack_internal $end
$var wire       1 #/   invert_arith_carry $end
$var wire       1 #0   io_initial_decode $end
$var reg     152 #1   kcpsm3_opcode [1:152] $end
$var reg     104 #2   kcpsm3_status [1:104] $end
$var wire      16 #3   kk_decode [1:16] $end
$var wire       8 #4   logical_result [7:0] $end
$var wire       8 #5   logical_value [7:0] $end
$var wire       1 #6   low_parity $end
$var wire       1 #7   low_shift_in $end
$var wire       1 #8   low_zero $end
$var wire       1 #9   low_zero_carry $end
$var wire       8 #:   memory_data [7:0] $end
$var wire       1 #;   memory_enable $end
$var wire       1 #<   memory_type $end
$var wire       1 #=   memory_write $end
$var wire       1 #>   move_group $end
$var wire       5 #?   next_stack_address [4:0] $end
$var wire       1 #@   normal_count $end
$var wire       1 #A   not_active_interrupt $end
$var wire       1 #B   not_t_state $end
$var wire       8 #C   out_port [7:0] $end
$var wire       1 #D   parity $end
$var wire       1 #E   parity_carry $end
$var wire      10 #F   pc [9:0] $end
$var wire       1 #G   pc_enable $end
$var wire      10 #H   pc_value [9:0] $end
$var wire       9 #I   pc_value_carry [8:0] $end
$var wire      10 #J   pc_vector [9:0] $end
$var wire       9 #K   pc_vector_carry [8:0] $end
$var wire       8 #L   port_id [7:0] $end
$var wire       1 #M   push_or_pop_type $end
$var wire       1 #N   read_active $end
$var wire       1 #O   read_strobe $end
$var wire       1 #P   register_enable $end
$var wire       1 #Q   register_type $end
$var wire       1 #R   register_write $end
$var wire       1 #S   reset $end
$var wire       1 #T   reset_delay $end
$var reg       8 #U   s0_contents [7:0] $end
$var reg       8 #V   s1_contents [7:0] $end
$var reg       8 #W   s2_contents [7:0] $end
$var reg       8 #X   s3_contents [7:0] $end
$var reg       8 #Y   s4_contents [7:0] $end
$var reg       8 #Z   s5_contents [7:0] $end
$var reg       8 #[   s6_contents [7:0] $end
$var reg       8 #\   s7_contents [7:0] $end
$var reg       8 #]   s8_contents [7:0] $end
$var reg       8 #^   s9_contents [7:0] $end
$var reg       8 #_   sa_contents [7:0] $end
$var reg       8 #`   sb_contents [7:0] $end
$var reg       8 #a   sc_contents [7:0] $end
$var reg       8 #b   sd_contents [7:0] $end
$var reg       8 #c   se_contents [7:0] $end
$var wire       8 #d   second_operand [7:0] $end
$var wire       1 #e   sel_arith $end
$var wire       1 #f   sel_arith_carry $end
$var wire       1 #g   sel_arith_carry_in $end
$var wire       4 #h   sel_carry [3:0] $end
$var wire       1 #i   sel_group $end
$var wire       1 #j   sel_logical $end
$var wire       1 #k   sel_parity $end
$var wire       1 #l   sel_shadow_carry $end
$var wire       1 #m   sel_shadow_zero $end
$var wire       1 #n   sel_shift $end
$var wire       1 #o   sel_shift_carry $end
$var reg       8 #p   sf_contents [7:0] $end
$var wire       1 #q   shadow_carry $end
$var wire       1 #r   shadow_zero $end
$var wire       1 #s   shift_carry $end
$var wire       1 #t   shift_carry_value $end
$var wire       1 #u   shift_in $end
$var wire       8 #v   shift_result [7:0] $end
$var wire       8 #w   shift_value [7:0] $end
$var reg       8 #x   spm00_contents [7:0] $end
$var reg       8 #y   spm01_contents [7:0] $end
$var reg       8 #z   spm02_contents [7:0] $end
$var reg       8 #{   spm03_contents [7:0] $end
$var reg       8 #|   spm04_contents [7:0] $end
$var reg       8 #}   spm05_contents [7:0] $end
$var reg       8 $!   spm06_contents [7:0] $end
$var reg       8 $"   spm07_contents [7:0] $end
$var reg       8 $#   spm08_contents [7:0] $end
$var reg       8 $$   spm09_contents [7:0] $end
$var reg       8 $%   spm0a_contents [7:0] $end
$var reg       8 $&   spm0b_contents [7:0] $end
$var reg       8 $'   spm0c_contents [7:0] $end
$var reg       8 $(   spm0d_contents [7:0] $end
$var reg       8 $)   spm0e_contents [7:0] $end
$var reg       8 $*   spm0f_contents [7:0] $end
$var reg       8 $+   spm10_contents [7:0] $end
$var reg       8 $,   spm11_contents [7:0] $end
$var reg       8 $-   spm12_contents [7:0] $end
$var reg       8 $.   spm13_contents [7:0] $end
$var reg       8 $/   spm14_contents [7:0] $end
$var reg       8 $0   spm15_contents [7:0] $end
$var reg       8 $1   spm16_contents [7:0] $end
$var reg       8 $2   spm17_contents [7:0] $end
$var reg       8 $3   spm18_contents [7:0] $end
$var reg       8 $4   spm19_contents [7:0] $end
$var reg       8 $5   spm1a_contents [7:0] $end
$var reg       8 $6   spm1b_contents [7:0] $end
$var reg       8 $7   spm1c_contents [7:0] $end
$var reg       8 $8   spm1d_contents [7:0] $end
$var reg       8 $9   spm1e_contents [7:0] $end
$var reg       8 $:   spm1f_contents [7:0] $end
$var reg       8 $;   spm20_contents [7:0] $end
$var reg       8 $<   spm21_contents [7:0] $end
$var reg       8 $=   spm22_contents [7:0] $end
$var reg       8 $>   spm23_contents [7:0] $end
$var reg       8 $?   spm24_contents [7:0] $end
$var reg       8 $@   spm25_contents [7:0] $end
$var reg       8 $A   spm26_contents [7:0] $end
$var reg       8 $B   spm27_contents [7:0] $end
$var reg       8 $C   spm28_contents [7:0] $end
$var reg       8 $D   spm29_contents [7:0] $end
$var reg       8 $E   spm2a_contents [7:0] $end
$var reg       8 $F   spm2b_contents [7:0] $end
$var reg       8 $G   spm2c_contents [7:0] $end
$var reg       8 $H   spm2d_contents [7:0] $end
$var reg       8 $I   spm2e_contents [7:0] $end
$var reg       8 $J   spm2f_contents [7:0] $end
$var reg       8 $K   spm30_contents [7:0] $end
$var reg       8 $L   spm31_contents [7:0] $end
$var reg       8 $M   spm32_contents [7:0] $end
$var reg       8 $N   spm33_contents [7:0] $end
$var reg       8 $O   spm34_contents [7:0] $end
$var reg       8 $P   spm35_contents [7:0] $end
$var reg       8 $Q   spm36_contents [7:0] $end
$var reg       8 $R   spm37_contents [7:0] $end
$var reg       8 $S   spm38_contents [7:0] $end
$var reg       8 $T   spm39_contents [7:0] $end
$var reg       8 $U   spm3a_contents [7:0] $end
$var reg       8 $V   spm3b_contents [7:0] $end
$var reg       8 $W   spm3c_contents [7:0] $end
$var reg       8 $X   spm3d_contents [7:0] $end
$var reg       8 $Y   spm3e_contents [7:0] $end
$var reg       8 $Z   spm3f_contents [7:0] $end
$var wire       5 $[   stack_address [4:0] $end
$var wire       4 $\   stack_address_carry [3:0] $end
$var wire      10 $]   stack_pop_data [9:0] $end
$var wire      10 $^   stack_ram_data [9:0] $end
$var wire       1 $_   stack_write_enable $end
$var wire       8 $`   store_data [7:0] $end
$var wire       8 $a   sx [7:0] $end
$var wire      16 $b   sx_decode [1:16] $end
$var wire       8 $c   sy [7:0] $end
$var wire      16 $d   sy_decode [1:16] $end
$var wire       1 $e   t_state $end
$var wire       1 $f   valid_to_move $end
$var wire       1 $g   write_active $end
$var wire       1 $h   write_strobe $end
$var wire       1 $i   zero_carry $end
$var wire       1 $j   zero_fast_route $end
$var wire       1 $k   zero_flag $end
$scope function hexcharacter $end
$var reg       8 $l   hexcharacter [1:8] $end
$var reg       4 $m   nibble [3:0] $end
$upscope $end
$scope module t_state_lut $end
$var wire       1 $n   I0 $end
$var wire       1 $p   O $end
$upscope $end
$scope module toggle_flop $end
$var wire       1 $r   C $end
$var wire       1 %3   D $end
$var tri0       1 %Q   GSR $end
$var reg       1 %o   Q $end
$var wire       1 &0   R $end
$upscope $end
$scope module reset_flop1 $end