Chapter 1. Creational Patterns Chapter 2. behavioral Patterns Chapter 3. Structural Patterns Chapter 4. System Patterns Chapter 5. Introduction to Java Programming Language Patterns Chapter 6. Java Core APIs Chapter 7. Distributed Technologies Chapter 8. Jini and J2EE Architectures
标签： Patterns Chapter behavioral Creational
上传时间： 2014-02-02
上传用户：bakdesec
PacoBlaze is a from-scratch synthesizable & behavioral Verilog clone of Ken Chapman s popular PicoBlaze embedded microcontroller. by Pablo Bleyer Kocik
标签： synthesizable from-scratch behavioral PacoBlaze
上传时间： 2013-12-09
上传用户：hphh
A software solution for the control of visual behavioral experimentation
标签： experimentation behavioral software solution
上传时间： 2013-12-21
上传用户：独孤求源
一篇优秀的博士论文,题目是 A particle swarm optimization based behavioral and probabilistic fire evacuation model incorporating fire hazards and human behaviors
标签： probabilistic optimization behavioral evacuation
上传时间： 2013-12-22
上传用户：waitingfy
arm10-behavioral的行为仿真代码ｖｅｒｉｌｏｇＨＤＬ
标签： behavioral arm 10 仿真
上传时间： 2014-11-05
上传用户：zhenyushaw
Booths Multiplier using behavioral Model
标签： behavioral Multiplier Booths Model
上传时间： 2017-05-21
上传用户：lmeeworm
Up-down Asynchronous counter in behavioral Model
标签： Asynchronous behavioral Up-down counter
上传时间： 2017-05-21
上传用户：caozhizhi
behavioral models are used in games and computer graphics for realistic simulation of massive crowds. In this paper, we present a GPU based implementation of Reynolds [1987] algorithm for simulating flocks of birds and propose an extension to consider environment self occlusion. We performed several experiments and the results showed that the proposed approach runs up to three times faster than the original algorithm when simulating high density crowds, without compromising significantly the original crowd behavior.
标签： behavioral simulation realistic computer
上传时间： 2017-09-08
上传用户：hanli8870
In this paper, we discuss efficient coding and design styles using verilog. This can beimmensely helpful for any digital designer initiating designs. Here, we address different problems rangingfrom RTL-Gate Level simulation mismatch to race conditions in writing behavioral models. All theseproblems are accompanied by an example to have a better idea, and these can be taken care off if thesecoding guidelines are followed. Discussion of all the techniques is beyond the scope of this paper, however,here we try to cover a few of them.
标签： Efficient Verilog Digital Coding
上传时间： 2013-11-22
上传用户：han_zh
怎样写testbench-xilinx 在ISE 环境中， 当前资源操作窗显示了资源管理窗口中选中的资源文件能进行的相关操作。在资源管理窗口选中了 testbench 文件后，在当前资源操作窗显示的 ModelSim Simulator 中显示了4种能进行的模拟操作，分别是：Simulator behavioral Model（功能仿真）、Simulator Post-translate VHDL Model（翻译后仿真）、Simulator Post-Map VHDL Model（映射后仿真）、Simulator Post-Place & Route VHDL Model（布局布线后仿真） 。如
标签： testbench-xilinx
上传时间： 2013-11-14
上传用户：467368609
