compare3_tb.vcd

来自「PacoBlaze is a from-scratch synthesizabl」· VCD 代码 · 共 2,065 行 · 第 1/5 页

$scope module memory_bit_2 $end
$var wire       1 6Z   A0 $end
$var wire       1 6b   A1 $end
$var wire       1 6j   A2 $end
$var wire       1 6r   A3 $end
$var wire       1 6z   A4 $end
$var wire       1 7%   A5 $end
$var wire       1 7-   D $end
$var wire       1 75   O $end
$var wire       1 7=   WCLK $end
$var wire       1 7E   WE $end
$var wire       6 7M   adr [5:0] $end
$var reg      64 7U   mem [63:0] $end
$upscope $end
$scope module store_flop_2 $end
$var wire       1 )p   C $end
$var wire       1 *+   D $end
$var tri0       1 *C   GSR $end
$var reg       1 *[   Q $end
$upscope $end
$scope module memory_bit_3 $end
$var wire       1 6[   A0 $end
$var wire       1 6c   A1 $end
$var wire       1 6k   A2 $end
$var wire       1 6s   A3 $end
$var wire       1 6{   A4 $end
$var wire       1 7&   A5 $end
$var wire       1 7.   D $end
$var wire       1 76   O $end
$var wire       1 7>   WCLK $end
$var wire       1 7F   WE $end
$var wire       6 7N   adr [5:0] $end
$var reg      64 7V   mem [63:0] $end
$upscope $end
$scope module store_flop_3 $end
$var wire       1 )q   C $end
$var wire       1 *,   D $end
$var tri0       1 *D   GSR $end
$var reg       1 *\   Q $end
$upscope $end
$scope module memory_bit_4 $end
$var wire       1 6\   A0 $end
$var wire       1 6d   A1 $end
$var wire       1 6l   A2 $end
$var wire       1 6t   A3 $end
$var wire       1 6|   A4 $end
$var wire       1 7'   A5 $end
$var wire       1 7/   D $end
$var wire       1 77   O $end
$var wire       1 7?   WCLK $end
$var wire       1 7G   WE $end
$var wire       6 7O   adr [5:0] $end
$var reg      64 7W   mem [63:0] $end
$upscope $end
$scope module store_flop_4 $end
$var wire       1 )r   C $end
$var wire       1 *-   D $end
$var tri0       1 *E   GSR $end
$var reg       1 *]   Q $end
$upscope $end
$scope module memory_bit_5 $end
$var wire       1 6]   A0 $end
$var wire       1 6e   A1 $end
$var wire       1 6m   A2 $end
$var wire       1 6u   A3 $end
$var wire       1 6}   A4 $end
$var wire       1 7(   A5 $end
$var wire       1 70   D $end
$var wire       1 78   O $end
$var wire       1 7@   WCLK $end
$var wire       1 7H   WE $end
$var wire       6 7P   adr [5:0] $end
$var reg      64 7X   mem [63:0] $end
$upscope $end
$scope module store_flop_5 $end
$var wire       1 )s   C $end
$var wire       1 *.   D $end
$var tri0       1 *F   GSR $end
$var reg       1 *^   Q $end
$upscope $end
$scope module memory_bit_6 $end
$var wire       1 6^   A0 $end
$var wire       1 6f   A1 $end
$var wire       1 6n   A2 $end
$var wire       1 6v   A3 $end
$var wire       1 7!   A4 $end
$var wire       1 7)   A5 $end
$var wire       1 71   D $end
$var wire       1 79   O $end
$var wire       1 7A   WCLK $end
$var wire       1 7I   WE $end
$var wire       6 7Q   adr [5:0] $end
$var reg      64 7Y   mem [63:0] $end
$upscope $end
$scope module store_flop_6 $end
$var wire       1 )t   C $end
$var wire       1 */   D $end
$var tri0       1 *G   GSR $end
$var reg       1 *_   Q $end
$upscope $end
$scope module memory_bit_7 $end
$var wire       1 6_   A0 $end
$var wire       1 6g   A1 $end
$var wire       1 6o   A2 $end
$var wire       1 6w   A3 $end
$var wire       1 7"   A4 $end
$var wire       1 7*   A5 $end
$var wire       1 72   D $end
$var wire       1 7:   O $end
$var wire       1 7B   WCLK $end
$var wire       1 7J   WE $end
$var wire       6 7R   adr [5:0] $end
$var reg      64 7Z   mem [63:0] $end
$upscope $end
$scope module store_flop_7 $end
$var wire       1 )u   C $end
$var wire       1 *0   D $end
$var tri0       1 *H   GSR $end
$var reg       1 *`   Q $end
$upscope $end
$scope module sel_logical_lut $end
$var wire       1 &g   I0 $end
$var wire       1 '+   I1 $end
$var wire       1 'L   I2 $end
$var wire       1 'm   I3 $end
$var reg       1 (1   O $end
$var reg       1 (R   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (s   d [3:0] $end
$var reg       1 )7   lut4_mux4 $end
$var reg       2 )X   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_lut_0 $end
$var wire       1 &h   I0 $end
$var wire       1 ',   I1 $end
$var wire       1 'M   I2 $end
$var wire       1 'n   I3 $end
$var reg       1 (2   O $end
$var reg       1 (S   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (t   d [3:0] $end
$var reg       1 )8   lut4_mux4 $end
$var reg       2 )Y   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_flop_0 $end
$var wire       1 $u   C $end
$var wire       1 %6   D $end
$var tri0       1 %T   GSR $end
$var reg       1 %r   Q $end
$var wire       1 &3   R $end
$upscope $end
$scope module logical_lut_1 $end
$var wire       1 &i   I0 $end
$var wire       1 '-   I1 $end
$var wire       1 'N   I2 $end
$var wire       1 'o   I3 $end
$var reg       1 (3   O $end
$var reg       1 (T   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (u   d [3:0] $end
$var reg       1 )9   lut4_mux4 $end
$var reg       2 )Z   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_flop_1 $end
$var wire       1 $v   C $end
$var wire       1 %7   D $end
$var tri0       1 %U   GSR $end
$var reg       1 %s   Q $end
$var wire       1 &4   R $end
$upscope $end
$scope module logical_lut_2 $end
$var wire       1 &j   I0 $end
$var wire       1 '.   I1 $end
$var wire       1 'O   I2 $end
$var wire       1 'p   I3 $end
$var reg       1 (4   O $end
$var reg       1 (U   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (v   d [3:0] $end
$var reg       1 ):   lut4_mux4 $end
$var reg       2 )[   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_flop_2 $end
$var wire       1 $w   C $end
$var wire       1 %8   D $end
$var tri0       1 %V   GSR $end
$var reg       1 %t   Q $end
$var wire       1 &5   R $end
$upscope $end
$scope module logical_lut_3 $end
$var wire       1 &k   I0 $end
$var wire       1 '/   I1 $end
$var wire       1 'P   I2 $end
$var wire       1 'q   I3 $end
$var reg       1 (5   O $end
$var reg       1 (V   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (w   d [3:0] $end
$var reg       1 );   lut4_mux4 $end
$var reg       2 )\   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_flop_3 $end
$var wire       1 $x   C $end
$var wire       1 %9   D $end
$var tri0       1 %W   GSR $end
$var reg       1 %u   Q $end
$var wire       1 &6   R $end
$upscope $end
$scope module logical_lut_4 $end
$var wire       1 &l   I0 $end
$var wire       1 '0   I1 $end
$var wire       1 'Q   I2 $end
$var wire       1 'r   I3 $end
$var reg       1 (6   O $end
$var reg       1 (W   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (x   d [3:0] $end
$var reg       1 )<   lut4_mux4 $end
$var reg       2 )]   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_flop_4 $end
$var wire       1 $y   C $end
$var wire       1 %:   D $end
$var tri0       1 %X   GSR $end
$var reg       1 %v   Q $end
$var wire       1 &7   R $end
$upscope $end
$scope module logical_lut_5 $end
$var wire       1 &m   I0 $end
$var wire       1 '1   I1 $end
$var wire       1 'R   I2 $end
$var wire       1 's   I3 $end
$var reg       1 (7   O $end
$var reg       1 (X   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (y   d [3:0] $end
$var reg       1 )=   lut4_mux4 $end
$var reg       2 )^   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_flop_5 $end
$var wire       1 $z   C $end
$var wire       1 %;   D $end
$var tri0       1 %Y   GSR $end
$var reg       1 %w   Q $end
$var wire       1 &8   R $end
$upscope $end
$scope module logical_lut_6 $end
$var wire       1 &n   I0 $end
$var wire       1 '2   I1 $end
$var wire       1 'S   I2 $end
$var wire       1 't   I3 $end
$var reg       1 (8   O $end
$var reg       1 (Y   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (z   d [3:0] $end
$var reg       1 )>   lut4_mux4 $end
$var reg       2 )_   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_flop_6 $end
$var wire       1 ${   C $end
$var wire       1 %<   D $end
$var tri0       1 %Z   GSR $end
$var reg       1 %x   Q $end
$var wire       1 &9   R $end
$upscope $end
$scope module logical_lut_7 $end
$var wire       1 &o   I0 $end
$var wire       1 '3   I1 $end
$var wire       1 'T   I2 $end
$var wire       1 'u   I3 $end
$var reg       1 (9   O $end
$var reg       1 (Z   tmp $end
$scope function lut4_mux4 $end
$var reg       4 ({   d [3:0] $end
$var reg       1 )?   lut4_mux4 $end
$var reg       2 )`   s [1:0] $end
$upscope $end
$upscope $end
$scope module logical_flop_7 $end
$var wire       1 $|   C $end
$var wire       1 %=   D $end
$var tri0       1 %[   GSR $end
$var reg       1 %y   Q $end
$var wire       1 &:   R $end
$upscope $end
$scope module sel_shift_inv $end
$var wire       1 4M   I $end
$var wire       1 4Q   O $end
$upscope $end
$scope module high_shift_in_lut $end
$var wire       1 +:   I0 $end
$var wire       1 ,"   I1 $end
$var wire       1 ,g   I2 $end
$var reg       1 -O   O $end
$var reg       1 .7   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .|   d [3:0] $end
$var reg       1 /d   lut3_mux4 $end
$var reg       2 0L   s [1:0] $end
$upscope $end
$upscope $end
$scope module low_shift_in_lut $end
$var wire       1 +;   I0 $end
$var wire       1 ,#   I1 $end
$var wire       1 ,h   I2 $end
$var reg       1 -P   O $end
$var reg       1 .8   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .}   d [3:0] $end
$var reg       1 /e   lut3_mux4 $end
$var reg       2 0M   s [1:0] $end
$upscope $end
$upscope $end
$scope module shift_in_muxf5 $end
$var wire       1 7[   I0 $end
$var wire       1 7d   I1 $end
$var reg       1 7m   O $end
$var wire       1 7v   S $end
$upscope $end
$scope module shift_carry_lut $end
$var wire       1 +<   I0 $end
$var wire       1 ,$   I1 $end
$var wire       1 ,i   I2 $end
$var reg       1 -Q   O $end
$var reg       1 .9   tmp $end
$scope function lut3_mux4 $end
$var reg       4 /!   d [3:0] $end
$var reg       1 /f   lut3_mux4 $end
$var reg       2 0N   s [1:0] $end
$upscope $end
$upscope $end
$scope module pipeline_bit $end
$var wire       1 )v   C $end
$var wire       1 *1   D $end
$var tri0       1 *I   GSR $end
$var reg       1 *a   Q $end
$upscope $end
$scope module shift_mux_lut_0 $end
$var wire       1 +=   I0 $end
$var wire       1 ,%   I1 $end
$var wire       1 ,j   I2 $end
$var reg       1 -R   O $end
$var reg       1 .:   tmp $end
$scope function lut3_mux4 $end
$var reg       4 /"   d [3:0] $end
$var reg       1 /g   lut3_mux4 $end
$var reg       2 0O   s [1:0] $end
$upscope $end
$upscope $end
$scope module shift_flop_0 $end
$var wire       1 $}   C $end
$var wire       1 %>   D $end
$var tri0       1 %\   GSR $end
$var reg       1 %z   Q $end
$var wire       1 &;   R $end
$upscope $end
$scope module shift_mux_lut_1 $end
$var wire       1 +>   I0 $end
$var wire       1 ,&   I1 $end
$var wire       1 ,k   I2 $end
$var reg       1 -S   O $end
$var reg       1 .;   tmp $end
$scope function lut3_mux4 $end
$var reg       4 /#   d [3:0] $end
$var reg       1 /h   lut3_mux4 $end
$var reg       2 0P   s [1:0] $end
$upscope $end
$upscope $end
$scope module shift_flop_1 $end
$var wire       1 %!   C $end
$var wire       1 %?   D $end
$var tri0       1 %]   GSR $end
$var reg       1 %{   Q $end
$var wire       1 &<   R $end
$upscope $end
$scope module shift_mux_lut_2 $end
$var wire       1 +?   I0 $end
$var wire       1 ,'   I1 $end
$var wire       1 ,l   I2 $end
$var reg       1 -T   O $end
$var reg       1 .<   tmp $end
$scope function lut3_mux4 $end
$var reg       4 /$   d [3:0] $end
$var reg       1 /i   lut3_mux4 $end
$var reg       2 0Q   s [1:0] $end
$upscope $end
$upscope $end
$scope module shift_flop_2 $end
$var wire       1 %"   C $end
$var wire       1 %@   D $end
$var tri0       1 %^   GSR $end
$var reg       1 %|   Q $end
$var wire       1 &=   R $end
$upscope $end
$scope module shift_mux_lut_3 $end
$var wire       1 +@   I0 $end
$var wire       1 ,(   I1 $end
$var wire       1 ,m   I2 $end
$var reg       1 -U   O $end
$var reg       1 .=   tmp $end
$scope function lut3_mux4 $end
$var reg       4 /%   d [3:0] $end
$var reg       1 /j   lut3_mux4 $end
$var reg       2 0R   s [1:0] $end
$upscope $end