compare3_tb.vcd

来自「PacoBlaze is a from-scratch synthesizabl」· VCD 代码 · 共 2,065 行 · 第 1/5 页

$var wire       1 +t   I1 $end
$var wire       1 ,\   I2 $end
$var reg       1 -D   O $end
$var reg       1 .,   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .q   d [3:0] $end
$var reg       1 /Y   lut3_mux4 $end
$var reg       2 0A   s [1:0] $end
$upscope $end
$upscope $end
$scope module pc_loop_register_bit_8 $end
$var wire       1 4\   C $end
$var wire       1 4f   CE $end
$var wire       1 4p   D $end
$var tri0       1 4z   GSR $end
$var reg       1 5'   Q $end
$var wire       1 51   R $end
$var wire       1 5;   S $end
$upscope $end
$scope module pc_vector_muxcy_8 $end
$var wire       1 1p   CI $end
$var wire       1 2:   DI $end
$var reg       1 2a   O $end
$var wire       1 3+   S $end
$upscope $end
$scope module pc_vector_xor_8 $end
$var wire       1 3M   CI $end
$var wire       1 3r   LI $end
$var wire       1 4:   O $end
$upscope $end
$scope module pc_value_muxcy_8 $end
$var wire       1 1q   CI $end
$var wire       1 2;   DI $end
$var reg       1 2b   O $end
$var wire       1 3,   S $end
$upscope $end
$scope module pc_value_xor_8 $end
$var wire       1 3N   CI $end
$var wire       1 3s   LI $end
$var wire       1 4;   O $end
$upscope $end
$scope module vector_select_mux_9 $end
$var wire       1 +0   I0 $end
$var wire       1 +u   I1 $end
$var wire       1 ,]   I2 $end
$var reg       1 -E   O $end
$var reg       1 .-   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .r   d [3:0] $end
$var reg       1 /Z   lut3_mux4 $end
$var reg       2 0B   s [1:0] $end
$upscope $end
$upscope $end
$scope module value_select_mux_9 $end
$var wire       1 +1   I0 $end
$var wire       1 +v   I1 $end
$var wire       1 ,^   I2 $end
$var reg       1 -F   O $end
$var reg       1 ..   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .s   d [3:0] $end
$var reg       1 /[   lut3_mux4 $end
$var reg       2 0C   s [1:0] $end
$upscope $end
$upscope $end
$scope module pc_loop_register_bit_9 $end
$var wire       1 4]   C $end
$var wire       1 4g   CE $end
$var wire       1 4q   D $end
$var tri0       1 4{   GSR $end
$var reg       1 5(   Q $end
$var wire       1 52   R $end
$var wire       1 5<   S $end
$upscope $end
$scope module pc_vector_xor_high $end
$var wire       1 3O   CI $end
$var wire       1 3t   LI $end
$var wire       1 4<   O $end
$upscope $end
$scope module pc_value_xor_high $end
$var wire       1 3P   CI $end
$var wire       1 3u   LI $end
$var wire       1 4=   O $end
$upscope $end
$scope module register_type_lut $end
$var wire       1 &d   I0 $end
$var wire       1 '(   I1 $end
$var wire       1 'I   I2 $end
$var wire       1 'j   I3 $end
$var reg       1 (.   O $end
$var reg       1 (O   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (p   d [3:0] $end
$var reg       1 )4   lut4_mux4 $end
$var reg       2 )U   s [1:0] $end
$upscope $end
$upscope $end
$scope module register_write_flop $end
$var wire       1 )l   C $end
$var wire       1 *'   D $end
$var tri0       1 *?   GSR $end
$var reg       1 *W   Q $end
$upscope $end
$scope module register_enable_lut $end
$var wire       1 1H   I0 $end
$var wire       1 1M   I1 $end
$var reg       1 1R   O $end
$var wire       2 1W   s [1:0] $end
$upscope $end
$scope module reg_loop_register_bit_0 $end
$var wire       1 5=   A0 $end
$var wire       1 5E   A1 $end
$var wire       1 5M   A2 $end
$var wire       1 5U   A3 $end
$var wire       1 5]   D $end
$var wire       1 5e   DPO $end
$var wire       1 5m   DPRA0 $end
$var wire       1 5u   DPRA1 $end
$var wire       1 5}   DPRA2 $end
$var wire       1 6(   DPRA3 $end
$var wire       1 60   SPO $end
$var wire       1 68   WCLK $end
$var wire       1 6@   WE $end
$var wire       4 6H   adr [3:0] $end
$var reg      16 6P   mem [15:0] $end
$upscope $end
$scope module operand_select_mux_0 $end
$var wire       1 +2   I0 $end
$var wire       1 +w   I1 $end
$var wire       1 ,_   I2 $end
$var reg       1 -G   O $end
$var reg       1 ./   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .t   d [3:0] $end
$var reg       1 /\   lut3_mux4 $end
$var reg       2 0D   s [1:0] $end
$upscope $end
$upscope $end
$scope module reg_loop_register_bit_1 $end
$var wire       1 5>   A0 $end
$var wire       1 5F   A1 $end
$var wire       1 5N   A2 $end
$var wire       1 5V   A3 $end
$var wire       1 5^   D $end
$var wire       1 5f   DPO $end
$var wire       1 5n   DPRA0 $end
$var wire       1 5v   DPRA1 $end
$var wire       1 6!   DPRA2 $end
$var wire       1 6)   DPRA3 $end
$var wire       1 61   SPO $end
$var wire       1 69   WCLK $end
$var wire       1 6A   WE $end
$var wire       4 6I   adr [3:0] $end
$var reg      16 6Q   mem [15:0] $end
$upscope $end
$scope module operand_select_mux_1 $end
$var wire       1 +3   I0 $end
$var wire       1 +x   I1 $end
$var wire       1 ,`   I2 $end
$var reg       1 -H   O $end
$var reg       1 .0   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .u   d [3:0] $end
$var reg       1 /]   lut3_mux4 $end
$var reg       2 0E   s [1:0] $end
$upscope $end
$upscope $end
$scope module reg_loop_register_bit_2 $end
$var wire       1 5?   A0 $end
$var wire       1 5G   A1 $end
$var wire       1 5O   A2 $end
$var wire       1 5W   A3 $end
$var wire       1 5_   D $end
$var wire       1 5g   DPO $end
$var wire       1 5o   DPRA0 $end
$var wire       1 5w   DPRA1 $end
$var wire       1 6"   DPRA2 $end
$var wire       1 6*   DPRA3 $end
$var wire       1 62   SPO $end
$var wire       1 6:   WCLK $end
$var wire       1 6B   WE $end
$var wire       4 6J   adr [3:0] $end
$var reg      16 6R   mem [15:0] $end
$upscope $end
$scope module operand_select_mux_2 $end
$var wire       1 +4   I0 $end
$var wire       1 +y   I1 $end
$var wire       1 ,a   I2 $end
$var reg       1 -I   O $end
$var reg       1 .1   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .v   d [3:0] $end
$var reg       1 /^   lut3_mux4 $end
$var reg       2 0F   s [1:0] $end
$upscope $end
$upscope $end
$scope module reg_loop_register_bit_3 $end
$var wire       1 5@   A0 $end
$var wire       1 5H   A1 $end
$var wire       1 5P   A2 $end
$var wire       1 5X   A3 $end
$var wire       1 5`   D $end
$var wire       1 5h   DPO $end
$var wire       1 5p   DPRA0 $end
$var wire       1 5x   DPRA1 $end
$var wire       1 6#   DPRA2 $end
$var wire       1 6+   DPRA3 $end
$var wire       1 63   SPO $end
$var wire       1 6;   WCLK $end
$var wire       1 6C   WE $end
$var wire       4 6K   adr [3:0] $end
$var reg      16 6S   mem [15:0] $end
$upscope $end
$scope module operand_select_mux_3 $end
$var wire       1 +5   I0 $end
$var wire       1 +z   I1 $end
$var wire       1 ,b   I2 $end
$var reg       1 -J   O $end
$var reg       1 .2   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .w   d [3:0] $end
$var reg       1 /_   lut3_mux4 $end
$var reg       2 0G   s [1:0] $end
$upscope $end
$upscope $end
$scope module reg_loop_register_bit_4 $end
$var wire       1 5A   A0 $end
$var wire       1 5I   A1 $end
$var wire       1 5Q   A2 $end
$var wire       1 5Y   A3 $end
$var wire       1 5a   D $end
$var wire       1 5i   DPO $end
$var wire       1 5q   DPRA0 $end
$var wire       1 5y   DPRA1 $end
$var wire       1 6$   DPRA2 $end
$var wire       1 6,   DPRA3 $end
$var wire       1 64   SPO $end
$var wire       1 6<   WCLK $end
$var wire       1 6D   WE $end
$var wire       4 6L   adr [3:0] $end
$var reg      16 6T   mem [15:0] $end
$upscope $end
$scope module operand_select_mux_4 $end
$var wire       1 +6   I0 $end
$var wire       1 +{   I1 $end
$var wire       1 ,c   I2 $end
$var reg       1 -K   O $end
$var reg       1 .3   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .x   d [3:0] $end
$var reg       1 /`   lut3_mux4 $end
$var reg       2 0H   s [1:0] $end
$upscope $end
$upscope $end
$scope module reg_loop_register_bit_5 $end
$var wire       1 5B   A0 $end
$var wire       1 5J   A1 $end
$var wire       1 5R   A2 $end
$var wire       1 5Z   A3 $end
$var wire       1 5b   D $end
$var wire       1 5j   DPO $end
$var wire       1 5r   DPRA0 $end
$var wire       1 5z   DPRA1 $end
$var wire       1 6%   DPRA2 $end
$var wire       1 6-   DPRA3 $end
$var wire       1 65   SPO $end
$var wire       1 6=   WCLK $end
$var wire       1 6E   WE $end
$var wire       4 6M   adr [3:0] $end
$var reg      16 6U   mem [15:0] $end
$upscope $end
$scope module operand_select_mux_5 $end
$var wire       1 +7   I0 $end
$var wire       1 +|   I1 $end
$var wire       1 ,d   I2 $end
$var reg       1 -L   O $end
$var reg       1 .4   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .y   d [3:0] $end
$var reg       1 /a   lut3_mux4 $end
$var reg       2 0I   s [1:0] $end
$upscope $end
$upscope $end
$scope module reg_loop_register_bit_6 $end
$var wire       1 5C   A0 $end
$var wire       1 5K   A1 $end
$var wire       1 5S   A2 $end
$var wire       1 5[   A3 $end
$var wire       1 5c   D $end
$var wire       1 5k   DPO $end
$var wire       1 5s   DPRA0 $end
$var wire       1 5{   DPRA1 $end
$var wire       1 6&   DPRA2 $end
$var wire       1 6.   DPRA3 $end
$var wire       1 66   SPO $end
$var wire       1 6>   WCLK $end
$var wire       1 6F   WE $end
$var wire       4 6N   adr [3:0] $end
$var reg      16 6V   mem [15:0] $end
$upscope $end
$scope module operand_select_mux_6 $end
$var wire       1 +8   I0 $end
$var wire       1 +}   I1 $end
$var wire       1 ,e   I2 $end
$var reg       1 -M   O $end
$var reg       1 .5   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .z   d [3:0] $end
$var reg       1 /b   lut3_mux4 $end
$var reg       2 0J   s [1:0] $end
$upscope $end
$upscope $end
$scope module reg_loop_register_bit_7 $end
$var wire       1 5D   A0 $end
$var wire       1 5L   A1 $end
$var wire       1 5T   A2 $end
$var wire       1 5\   A3 $end
$var wire       1 5d   D $end
$var wire       1 5l   DPO $end
$var wire       1 5t   DPRA0 $end
$var wire       1 5|   DPRA1 $end
$var wire       1 6'   DPRA2 $end
$var wire       1 6/   DPRA3 $end
$var wire       1 67   SPO $end
$var wire       1 6?   WCLK $end
$var wire       1 6G   WE $end
$var wire       4 6O   adr [3:0] $end
$var reg      16 6W   mem [15:0] $end
$upscope $end
$scope module operand_select_mux_7 $end
$var wire       1 +9   I0 $end
$var wire       1 ,!   I1 $end
$var wire       1 ,f   I2 $end
$var reg       1 -N   O $end
$var reg       1 .6   tmp $end
$scope function lut3_mux4 $end
$var reg       4 .{   d [3:0] $end
$var reg       1 /c   lut3_mux4 $end
$var reg       2 0K   s [1:0] $end
$upscope $end
$upscope $end
$scope module memory_type_lut $end
$var wire       1 &e   I0 $end
$var wire       1 ')   I1 $end
$var wire       1 'J   I2 $end
$var wire       1 'k   I3 $end
$var reg       1 (/   O $end
$var reg       1 (P   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (q   d [3:0] $end
$var reg       1 )5   lut4_mux4 $end
$var reg       2 )V   s [1:0] $end
$upscope $end
$upscope $end
$scope module memory_write_flop $end
$var wire       1 )m   C $end
$var wire       1 *(   D $end
$var tri0       1 *@   GSR $end
$var reg       1 *X   Q $end
$upscope $end
$scope module memory_enable_lut $end
$var wire       1 &f   I0 $end
$var wire       1 '*   I1 $end
$var wire       1 'K   I2 $end
$var wire       1 'l   I3 $end
$var reg       1 (0   O $end
$var reg       1 (Q   tmp $end
$scope function lut4_mux4 $end
$var reg       4 (r   d [3:0] $end
$var reg       1 )6   lut4_mux4 $end
$var reg       2 )W   s [1:0] $end
$upscope $end
$upscope $end
$scope module memory_bit_0 $end
$var wire       1 6X   A0 $end
$var wire       1 6`   A1 $end
$var wire       1 6h   A2 $end
$var wire       1 6p   A3 $end
$var wire       1 6x   A4 $end
$var wire       1 7#   A5 $end
$var wire       1 7+   D $end
$var wire       1 73   O $end
$var wire       1 7;   WCLK $end
$var wire       1 7C   WE $end
$var wire       6 7K   adr [5:0] $end
$var reg      64 7S   mem [63:0] $end
$upscope $end
$scope module store_flop_0 $end
$var wire       1 )n   C $end
$var wire       1 *)   D $end
$var tri0       1 *A   GSR $end
$var reg       1 *Y   Q $end
$upscope $end
$scope module memory_bit_1 $end
$var wire       1 6Y   A0 $end
$var wire       1 6a   A1 $end
$var wire       1 6i   A2 $end
$var wire       1 6q   A3 $end
$var wire       1 6y   A4 $end
$var wire       1 7$   A5 $end
$var wire       1 7,   D $end
$var wire       1 74   O $end
$var wire       1 7<   WCLK $end
$var wire       1 7D   WE $end
$var wire       6 7L   adr [5:0] $end
$var reg      64 7T   mem [63:0] $end
$upscope $end
$scope module store_flop_1 $end
$var wire       1 )o   C $end
$var wire       1 **   D $end
$var tri0       1 *B   GSR $end
$var reg       1 *Z   Q $end
$upscope $end