crc_top_syn.vhd

来自「一个verilog实现的crc校验」· VHDL 代码 · 共 1,346 行 · 第 1/5 页

   
   component BU4
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   signal n75, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118
      , n119, n120, n121, n122, n123 : std_logic;

begin
   
   output_reg_15 : DFA2 port map( C => phi2, D => input(0), Q => output(0), QN 
                           => n108, RN => n75);
   output_reg_14 : DFA2 port map( C => phi2, D => input(1), Q => output(1), QN 
                           => n109, RN => n75);
   output_reg_13 : DFA2 port map( C => phi2, D => input(2), Q => output(2), QN 
                           => n110, RN => n75);
   output_reg_12 : DFA2 port map( C => phi2, D => input(3), Q => output(3), QN 
                           => n111, RN => n75);
   output_reg_11 : DFA2 port map( C => phi2, D => input(4), Q => output(4), QN 
                           => n112, RN => n75);
   output_reg_10 : DFA2 port map( C => phi2, D => input(5), Q => output(5), QN 
                           => n113, RN => n75);
   output_reg_9 : DFA2 port map( C => phi2, D => input(6), Q => output(6), QN 
                           => n114, RN => n75);
   output_reg_8 : DFA2 port map( C => phi2, D => input(7), Q => output(7), QN 
                           => n115, RN => n75);
   output_reg_7 : DFA2 port map( C => phi2, D => input(8), Q => output(8), QN 
                           => n116, RN => n75);
   output_reg_6 : DFA2 port map( C => phi2, D => input(9), Q => output(9), QN 
                           => n117, RN => n75);
   output_reg_5 : DFA2 port map( C => phi2, D => input(10), Q => output(10), QN
                           => n118, RN => n75);
   output_reg_4 : DFA2 port map( C => phi2, D => input(11), Q => output(11), QN
                           => n119, RN => n75);
   output_reg_3 : DFA2 port map( C => phi2, D => input(12), Q => output(12), QN
                           => n120, RN => n75);
   output_reg_2 : DFA2 port map( C => phi2, D => input(13), Q => output(13), QN
                           => n121, RN => n75);
   output_reg_1 : DFA2 port map( C => phi2, D => input(14), Q => output(14), QN
                           => n122, RN => n75);
   output_reg_0 : DFA2 port map( C => phi2, D => input(15), Q => output(15), QN
                           => n123, RN => n75);
   U48 : BU4 port map( A => reset, Q => n75);

end SYN_behavior_0;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_phi2_register_1 is

   port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);  
         output : out std_logic_vector (0 to 15));

end input_phi2_register_1;

architecture SYN_behavior_1 of input_phi2_register_1 is

   component DFA
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   component DFA2
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   component BU2
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   signal n82, n115, n116, n117, n118, n119, n120, n121, n122, n123, n124, n125
      , n126, n127, n128, n129, n130 : std_logic;

begin
   
   output_reg_15 : DFA port map( C => phi2, D => input(0), Q => output(0), QN 
                           => n115, RN => n82);
   output_reg_14 : DFA port map( C => phi2, D => input(1), Q => output(1), QN 
                           => n116, RN => n82);
   output_reg_13 : DFA2 port map( C => phi2, D => input(2), Q => output(2), QN 
                           => n117, RN => reset);
   output_reg_12 : DFA2 port map( C => phi2, D => input(3), Q => output(3), QN 
                           => n118, RN => reset);
   output_reg_11 : DFA2 port map( C => phi2, D => input(4), Q => output(4), QN 
                           => n119, RN => reset);
   output_reg_10 : DFA2 port map( C => phi2, D => input(5), Q => output(5), QN 
                           => n120, RN => reset);
   output_reg_9 : DFA2 port map( C => phi2, D => input(6), Q => output(6), QN 
                           => n121, RN => reset);
   output_reg_8 : DFA2 port map( C => phi2, D => input(7), Q => output(7), QN 
                           => n122, RN => reset);
   output_reg_7 : DFA2 port map( C => phi2, D => input(8), Q => output(8), QN 
                           => n123, RN => reset);
   output_reg_6 : DFA port map( C => phi2, D => input(9), Q => output(9), QN =>
                           n124, RN => n82);
   output_reg_5 : DFA2 port map( C => phi2, D => input(10), Q => output(10), QN
                           => n125, RN => reset);
   output_reg_4 : DFA2 port map( C => phi2, D => input(11), Q => output(11), QN
                           => n126, RN => reset);
   output_reg_3 : DFA2 port map( C => phi2, D => input(12), Q => output(12), QN
                           => n127, RN => reset);
   output_reg_2 : DFA port map( C => phi2, D => input(13), Q => output(13), QN 
                           => n128, RN => n82);
   output_reg_1 : DFA2 port map( C => phi2, D => input(14), Q => output(14), QN
                           => n129, RN => reset);
   output_reg_0 : DFA2 port map( C => phi2, D => input(15), Q => output(15), QN
                           => n130, RN => reset);
   U48 : BU2 port map( A => reset, Q => n82);

end SYN_behavior_1;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_phi2_register_2 is

   port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);  
         output : out std_logic_vector (0 to 15));

end input_phi2_register_2;

architecture SYN_behavior_2 of input_phi2_register_2 is

   component DFA2
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   component DFA
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   signal n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, 
      n118, n119, n120, n121, n122 : std_logic;

begin
   
   output_reg_15 : DFA2 port map( C => phi2, D => input(0), Q => output(0), QN 
                           => n107, RN => reset);
   output_reg_14 : DFA2 port map( C => phi2, D => input(1), Q => output(1), QN 
                           => n108, RN => reset);
   output_reg_13 : DFA2 port map( C => phi2, D => input(2), Q => output(2), QN 
                           => n109, RN => reset);
   output_reg_12 : DFA2 port map( C => phi2, D => input(3), Q => output(3), QN 
                           => n110, RN => reset);
   output_reg_11 : DFA2 port map( C => phi2, D => input(4), Q => output(4), QN 
                           => n111, RN => reset);
   output_reg_10 : DFA2 port map( C => phi2, D => input(5), Q => output(5), QN 
                           => n112, RN => reset);
   output_reg_9 : DFA2 port map( C => phi2, D => input(6), Q => output(6), QN 
                           => n113, RN => reset);
   output_reg_8 : DFA2 port map( C => phi2, D => input(7), Q => output(7), QN 
                           => n114, RN => reset);
   output_reg_7 : DFA2 port map( C => phi2, D => input(8), Q => output(8), QN 
                           => n115, RN => reset);
   output_reg_6 : DFA2 port map( C => phi2, D => input(9), Q => output(9), QN 
                           => n116, RN => reset);
   output_reg_5 : DFA2 port map( C => phi2, D => input(10), Q => output(10), QN
                           => n117, RN => reset);
   output_reg_4 : DFA port map( C => phi2, D => input(11), Q => output(11), QN 
                           => n118, RN => reset);
   output_reg_3 : DFA port map( C => phi2, D => input(12), Q => output(12), QN 
                           => n119, RN => reset);
   output_reg_2 : DFA port map( C => phi2, D => input(13), Q => output(13), QN 
                           => n120, RN => reset);
   output_reg_1 : DFA port map( C => phi2, D => input(14), Q => output(14), QN 
                           => n121, RN => reset);
   output_reg_0 : DFA port map( C => phi2, D => input(15), Q => output(15), QN 
                           => n122, RN => reset);

end SYN_behavior_2;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_phi2_register_3 is

   port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);  
         output : out std_logic_vector (0 to 15));

end input_phi2_register_3;

architecture SYN_behavior_3 of input_phi2_register_3 is

   component IN3
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   component DFA
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   component IN1
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   signal n97, n99, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141,
      n142, n143, n144, n145, n146, n147 : std_logic;

begin
   
   U48 : IN3 port map( A => n97, Q => n99);
   output_reg_15 : DFA port map( C => phi2, D => input(0), Q => output(0), QN 
                           => n132, RN => n99);
   output_reg_14 : DFA port map( C => phi2, D => input(1), Q => output(1), QN 
                           => n133, RN => n99);
   output_reg_13 : DFA port map( C => phi2, D => input(2), Q => output(2), QN 
                           => n134, RN => n99);
   output_reg_12 : DFA port map( C => phi2, D => input(3), Q => output(3), QN 
                           => n135, RN => n99);
   output_reg_11 : DFA port map( C => phi2, D => input(4), Q => output(4), QN 
                           => n136, RN => n99);
   output_reg_10 : DFA port map( C => phi2, D => input(5), Q => output(5), QN 
                           => n137, RN => n99);
   output_reg_9 : DFA port map( C => phi2, D => input(6), Q => output(6), QN =>
                           n138, RN => n99);
   output_reg_8 : DFA port map( C => phi2, D => input(7), Q => output(7), QN =>
                           n139, RN => n99);
   output_reg_7 : DFA port map( C => phi2, D => input(8), Q => output(8), QN =>
                           n140, RN => n99);
   output_reg_6 : DFA port map( C => phi2, D => input(9), Q => output(9), QN =>
                           n141, RN => n99);
   output_reg_5 : DFA port map( C => phi2, D => input(10), Q => output(10), QN 
                           => n142, RN => n99);
   output_reg_4 : DFA port map( C => phi2, D => input(11), Q => output(11), QN 
                           => n143, RN => n99);
   output_reg_3 : DFA port map( C => phi2, D => input(12), Q => output(12), QN 
                           => n144, RN => n99);
   output_reg_2 : DFA port map( C => phi2, D => input(13), Q => output(13), QN 
                           => n145, RN => n99);
   output_reg_1 : DFA port map( C => phi2, D => input(14), Q => output(14), QN 
                           => n146, RN => n99);
   output_reg_0 : DFA port map( C => phi2, D => input(15), Q => output(15), QN 
                           => n147, RN => n99);
   U49 : IN1 port map( A => reset, Q => n97);

end SYN_behavior_3;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_phi1_register_0 is

   port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);  
         output : out std_logic_vector (0 to 15));

end input_phi1_register_0;