crc_top_syn.vhd

来自「一个verilog实现的crc校验」· VHDL 代码 · 共 1,346 行 · 第 1/5 页

   output_reg_11 : DFA2 port map( C => phi1, D => input(4), Q => n221, QN => 
                           n135, RN => n90);
   U63 : IN4 port map( A => n139, Q => output(8));
   output_reg_7 : DFA2 port map( C => phi1, D => input(8), Q => n222, QN => 
                           n139, RN => n90);
   U64 : IN4 port map( A => n157, Q => output(14));
   output_reg_1 : DFA2 port map( C => phi1, D => input(14), Q => n223, QN => 
                           n157, RN => n90);
   U65 : IN4 port map( A => n159, Q => output(7));
   output_reg_8 : DFA2 port map( C => phi1, D => input(7), Q => n224, QN => 
                           n159, RN => n90);

end SYN_behavior_3;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_wait is

   port( phi1, phi2, reset : in std_logic;  input : in std_logic_vector (0 to 
         15);  output : out std_logic_vector (0 to 15));

end input_wait;

architecture SYN_structural_architecture of input_wait is

   component input_phi2_register_0
      port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
            output : out std_logic_vector (0 to 15));
   end component;
   
   component input_phi2_register_1
      port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
            output : out std_logic_vector (0 to 15));
   end component;
   
   component input_phi2_register_2
      port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
            output : out std_logic_vector (0 to 15));
   end component;
   
   component input_phi2_register_3
      port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);
            output : out std_logic_vector (0 to 15));
   end component;
   
   component input_phi1_register_0
      port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
            output : out std_logic_vector (0 to 15));
   end component;
   
   component input_phi1_register_1
      port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
            output : out std_logic_vector (0 to 15));
   end component;
   
   component input_phi1_register_2
      port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
            output : out std_logic_vector (0 to 15));
   end component;
   
   component input_phi1_register_3
      port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);
            output : out std_logic_vector (0 to 15));
   end component;
   
   signal btw1and2_12, btw1and2_7, btw6and7_11, btw3and4_9, btw4and5_1, 
      btw5and6_14, btw5and6_4, btw6and7_9, btw7and8_2, btw2and3_10, btw2and3_3,
      btw7and8_12, btw3and4_7, btw3and4_0, btw4and5_14, btw4and5_8, btw6and7_0,
      btw6and7_7, btw3and4_11, btw4and5_13, btw1and2_15, btw1and2_9, btw2and3_4
      , btw7and8_15, btw5and6_3, btw7and8_5, btw1and2_14, btw1and2_0, 
      btw4and5_6, btw5and6_13, btw1and2_13, btw1and2_8, btw7and8_4, btw1and2_6,
      btw1and2_1, btw2and3_11, btw2and3_5, btw7and8_14, btw3and4_10, btw3and4_6
      , btw4and5_12, btw6and7_6, btw4and5_7, btw5and6_12, btw3and4_8, 
      btw5and6_2, btw5and6_5, btw6and7_8, btw4and5_0, btw5and6_15, btw3and4_1, 
      btw6and7_10, btw4and5_15, btw6and7_1, btw4and5_9, btw2and3_2, btw7and8_13
      , btw7and8_3, btw1and2_11, btw1and2_4, btw2and3_9, btw6and7_12, 
      btw7and8_8, btw4and5_2, btw5and6_7, btw1and2_10, btw1and2_5, btw1and2_3, 
      btw2and3_14, btw2and3_0, btw7and8_11, btw7and8_1, btw3and4_15, 
      btw2and3_13, btw3and4_4, btw3and4_3, btw6and7_3, btw5and6_9, btw6and7_4, 
      btw2and3_7, btw3and4_12, btw4and5_10, btw4and5_5, btw5and6_10, btw5and6_0
      , btw7and8_6, btw1and2_2, btw2and3_12, btw2and3_6, btw6and7_15, 
      btw7and8_7, btw3and4_13, btw3and4_5, btw4and5_11, btw5and6_8, btw6and7_5,
      btw6and7_14, btw4and5_4, btw5and6_11, btw5and6_6, btw5and6_1, btw2and3_8,
      btw4and5_3, btw2and3_15, btw3and4_14, btw3and4_2, btw6and7_13, btw6and7_2
      , btw7and8_9, btw2and3_1, btw7and8_10, btw7and8_0 : std_logic;

begin
   
   Input1 : input_phi2_register_3 port map( reset => reset, phi2 => phi2, 
                           input(0) => input(0), input(1) => input(1), input(2)
                           => input(2), input(3) => input(3), input(4) => 
                           input(4), input(5) => input(5), input(6) => input(6)
                           , input(7) => input(7), input(8) => input(8), 
                           input(9) => input(9), input(10) => input(10), 
                           input(11) => input(11), input(12) => input(12), 
                           input(13) => input(13), input(14) => input(14), 
                           input(15) => input(15), output(0) => btw1and2_15, 
                           output(1) => btw1and2_14, output(2) => btw1and2_13, 
                           output(3) => btw1and2_12, output(4) => btw1and2_11, 
                           output(5) => btw1and2_10, output(6) => btw1and2_9, 
                           output(7) => btw1and2_8, output(8) => btw1and2_7, 
                           output(9) => btw1and2_6, output(10) => btw1and2_5, 
                           output(11) => btw1and2_4, output(12) => btw1and2_3, 
                           output(13) => btw1and2_2, output(14) => btw1and2_1, 
                           output(15) => btw1and2_0);
   Input8 : input_phi1_register_3 port map( reset => reset, phi1 => phi1, 
                           input(0) => btw7and8_15, input(1) => btw7and8_14, 
                           input(2) => btw7and8_13, input(3) => btw7and8_12, 
                           input(4) => btw7and8_11, input(5) => btw7and8_10, 
                           input(6) => btw7and8_9, input(7) => btw7and8_8, 
                           input(8) => btw7and8_7, input(9) => btw7and8_6, 
                           input(10) => btw7and8_5, input(11) => btw7and8_4, 
                           input(12) => btw7and8_3, input(13) => btw7and8_2, 
                           input(14) => btw7and8_1, input(15) => btw7and8_0, 
                           output(0) => output(0), output(1) => output(1), 
                           output(2) => output(2), output(3) => output(3), 
                           output(4) => output(4), output(5) => output(5), 
                           output(6) => output(6), output(7) => output(7), 
                           output(8) => output(8), output(9) => output(9), 
                           output(10) => output(10), output(11) => output(11), 
                           output(12) => output(12), output(13) => output(13), 
                           output(14) => output(14), output(15) => output(15));
   Input2 : input_phi1_register_2 port map( reset => reset, phi1 => phi1, 
                           input(0) => btw1and2_15, input(1) => btw1and2_14, 
                           input(2) => btw1and2_13, input(3) => btw1and2_12, 
                           input(4) => btw1and2_11, input(5) => btw1and2_10, 
                           input(6) => btw1and2_9, input(7) => btw1and2_8, 
                           input(8) => btw1and2_7, input(9) => btw1and2_6, 
                           input(10) => btw1and2_5, input(11) => btw1and2_4, 
                           input(12) => btw1and2_3, input(13) => btw1and2_2, 
                           input(14) => btw1and2_1, input(15) => btw1and2_0, 
                           output(0) => btw2and3_15, output(1) => btw2and3_14, 
                           output(2) => btw2and3_13, output(3) => btw2and3_12, 
                           output(4) => btw2and3_11, output(5) => btw2and3_10, 
                           output(6) => btw2and3_9, output(7) => btw2and3_8, 
                           output(8) => btw2and3_7, output(9) => btw2and3_6, 
                           output(10) => btw2and3_5, output(11) => btw2and3_4, 
                           output(12) => btw2and3_3, output(13) => btw2and3_2, 
                           output(14) => btw2and3_1, output(15) => btw2and3_0);
   Input6 : input_phi1_register_1 port map( reset => reset, phi1 => phi1, 
                           input(0) => btw5and6_15, input(1) => btw5and6_14, 
                           input(2) => btw5and6_13, input(3) => btw5and6_12, 
                           input(4) => btw5and6_11, input(5) => btw5and6_10, 
                           input(6) => btw5and6_9, input(7) => btw5and6_8, 
                           input(8) => btw5and6_7, input(9) => btw5and6_6, 
                           input(10) => btw5and6_5, input(11) => btw5and6_4, 
                           input(12) => btw5and6_3, input(13) => btw5and6_2, 
                           input(14) => btw5and6_1, input(15) => btw5and6_0, 
                           output(0) => btw6and7_15, output(1) => btw6and7_14, 
                           output(2) => btw6and7_13, output(3) => btw6and7_12, 
                           output(4) => btw6and7_11, output(5) => btw6and7_10, 
                           output(6) => btw6and7_9, output(7) => btw6and7_8, 
                           output(8) => btw6and7_7, output(9) => btw6and7_6, 
                           output(10) => btw6and7_5, output(11) => btw6and7_4, 
                           output(12) => btw6and7_3, output(13) => btw6and7_2, 
                           output(14) => btw6and7_1, output(15) => btw6and7_0);
   Input7 : input_phi2_register_2 port map( reset => reset, phi2 => phi2, 
                           input(0) => btw6and7_15, input(1) => btw6and7_14, 
                           input(2) => btw6and7_13, input(3) => btw6and7_12, 
                           input(4) => btw6and7_11, input(5) => btw6and7_10, 
                           input(6) => btw6and7_9, input(7) => btw6and7_8, 
                           input(8) => btw6and7_7, input(9) => btw6and7_6, 
                           input(10) => btw6and7_5, input(11) => btw6and7_4, 
                           input(12) => btw6and7_3, input(13) => btw6and7_2, 
                           input(14) => btw6and7_1, input(15) => btw6and7_0, 
                           output(0) => btw7and8_15, output(1) => btw7and8_14, 
                           output(2) => btw7and8_13, output(3) => btw7and8_12, 
                           output(4) => btw7and8_11, output(5) => btw7and8_10, 
                           output(6) => btw7and8_9, output(7) => btw7and8_8, 
                           output(8) => btw7and8_7, output(9) => btw7and8_6, 
                           output(10) => btw7and8_5, output(11) => btw7and8_4, 
                           output(12) => btw7and8_3, output(13) => btw7and8_2, 
                           output(14) => btw7and8_1, output(15) => btw7and8_0);
   Input3 : input_phi2_register_1 port map( reset => reset, phi2 => phi2, 
                           input(0) => btw2and3_15, input(1) => btw2and3_14, 
                           input(2) => btw2and3_13, input(3) => btw2and3_12, 
                           input(4) => btw2and3_11, input(5) => btw2and3_10, 
                           input(6) => btw2and3_9, input(7) => btw2and3_8, 
                           input(8) => btw2and3_7, input(9) => btw2and3_6, 
                           input(10) => btw2and3_5, input(11) => btw2and3_4, 
                           input(12) => btw2and3_3, input(13) => btw2and3_2, 
                           input(14) => btw2and3_1, input(15) => btw2and3_0, 
                           output(0) => btw3and4_15, output(1) => btw3and4_14, 
                           output(2) => btw3and4_13, output(3) => btw3and4_12, 
                           output(4) => btw3and4_11, output(5) => btw3and4_10, 
                           output(6) => btw3and4_9, output(7) => btw3and4_8, 
                           output(8) => btw3and4_7, output(9) => btw3and4_6, 
                           output(10) => btw3and4_5, output(11) => btw3and4_4, 
                           output(12) => btw3and4_3, output(13) => btw3and4_2, 
                           output(14) => btw3and4_1, output(15) => btw3and4_0);
   Input4 : input_phi1_register_0 port map( reset => reset, phi1 => phi1, 
                           input(0) => btw3and4_15, input(1) => btw3and4_14, 
                           input(2) => btw3and4_13, input(3) => btw3and4_12, 
                           input(4) => btw3and4_11, input(5) => btw3and4_10, 
                           input(6) => btw3and4_9, input(7) => btw3and4_8, 
                           input(8) => btw3and4_7, input(9) => btw3and4_6, 
                           input(10) => btw3and4_5, input(11) => btw3and4_4, 
                           input(12) => btw3and4_3, input(13) => btw3and4_2, 
                           input(14) => btw3and4_1, input(15) => btw3and4_0, 
                           output(0) => btw4and5_15, output(1) => btw4and5_14, 
                           output(2) => btw4and5_13, output(3) => btw4and5_12, 
                           output(4) => btw4and5_11, output(5) => btw4and5_10, 
                           output(6) => btw4and5_9, output(7) => btw4and5_8, 
                           output(8) => btw4and5_7, output(9) => btw4and5_6, 
                           output(10) => btw4and5_5, output(11) => btw4and5_4, 
                           output(12) => btw4and5_3, output(13) => btw4and5_2, 
                           output(14) => btw4and5_1, output(15) => btw4and5_0);
   Input5 : input_phi2_register_0 port map( reset => reset, phi2 => phi2, 
                           input(0) => btw4and5_15, input(1) => btw4and5_14, 
                           input(2) => btw4and5_13, input(3) => btw4and5_12, 
                           input(4) => btw4and5_11, input(5) => btw4and5_10, 
                           input(6) => btw4and5_9, input(7) => btw4and5_8, 
                           input(8) => btw4and5_7, input(9) => btw4and5_6, 
                           input(10) => btw4and5_5, input(11) => btw4and5_4, 
                           input(12) => btw4and5_3, input(13) => btw4and5_2, 
                           input(14) => btw4and5_1, input(15) => btw4and5_0, 
                           output(0) => btw5and6_15, output(1) => btw5and6_14, 
                           output(2) => btw5and6_13, output(3) => btw5and6_12, 
                           output(4) => btw5and6_11, output(5) => btw5and6_10, 
                           output(6) => btw5and6_9, output(7) => btw5and6_8, 
                           output(8) => btw5and6_7, output(9) => btw5and6_6, 
                           output(10) => btw5and6_5, output(11) => btw5and6_4, 
                           output(12) => btw5and6_3, output(13) => btw5and6_2, 
                           output(14) => btw5and6_1, output(15) => btw5and6_0);

end SYN_structural_architecture;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity gf_xor_input is

   port( input_fcs : in std_logic_vector (0 to 31);  output_wip : out 
         std_logic_vector (0 to 31));

end gf_xor_input;

architecture SYN_behavior of gf_xor_input is

   component EO1
      port( A, B : in std_logic;  Q : out std_logic);
   end component;
   
   signal output_wip_22, output_wip_6, output_wip_28, output_wip_8, 
      output_wip_26, output_wip_27, output_wip_20, output_wip_0, output_wip_7, 
      output_wip_29, net8524, output_wip_11, output_wip_14, net8460, 
      output_wip_4, net6785, output_wip_31, output_wip_23, output_wip_5, 
      output_wip_9 : std_logic;

begin
   output_wip <= ( output_wip_31, net6785, output_wip_29, output_wip_28, 
      output_wip_27, output_wip_26, output_wip_31, net6785, output_wip_23, 
      output_wip_22, output_wip_5, output_wip_20, output_wip_31, output_wip_11,
      net8460, output_wip_9, output_wip_4, output_wip_14, net8460, 
      output_wip_23, output_wip_11, net8524, output_wip_9, output_wip_8, 
      output_wip_7, output_wip_6, output_wip_5, output_wip_4, output_wip_14, 
      net8524, output_wip_9, output_wip_0 );