crc_top_syn.vhd

来自「一个verilog实现的crc校验」· VHDL 代码 · 共 1,346 行 · 第 1/5 页

   
   U7 : EO1 port map( A => input_fcs(1), B => input_fcs(2), Q => net8524);
   U8 : EO1 port map( A => input_fcs(1), B => input_fcs(2), Q => net8460);
   U9 : EO1 port map( A => input_fcs(1), B => input_fcs(5), Q => net6785);
   U10 : EO1 port map( A => input_fcs(7), B => input_fcs(3), Q => output_wip_28
                           );
   U11 : EO1 port map( A => input_fcs(5), B => input_fcs(9), Q => output_wip_26
                           );
   U12 : EO1 port map( A => input_fcs(5), B => input_fcs(3), Q => output_wip_0)
                           ;
   U13 : EO1 port map( A => input_fcs(1), B => input_fcs(0), Q => output_wip_11
                           );
   U14 : EO1 port map( A => input_fcs(1), B => input_fcs(0), Q => output_wip_14
                           );
   U15 : EO1 port map( A => input_fcs(4), B => input_fcs(8), Q => output_wip_27
                           );
   U16 : EO1 port map( A => input_fcs(3), B => input_fcs(6), Q => output_wip_20
                           );
   U17 : EO1 port map( A => input_fcs(3), B => input_fcs(4), Q => output_wip_8)
                           ;
   U18 : EO1 port map( A => input_fcs(1), B => input_fcs(3), Q => output_wip_22
                           );
   U19 : EO1 port map( A => input_fcs(1), B => input_fcs(4), Q => output_wip_6)
                           ;
   U20 : EO1 port map( A => input_fcs(2), B => input_fcs(6), Q => output_wip_29
                           );
   U21 : EO1 port map( A => input_fcs(2), B => input_fcs(3), Q => output_wip_9)
                           ;
   U22 : EO1 port map( A => input_fcs(2), B => input_fcs(5), Q => output_wip_5)
                           ;
   U23 : EO1 port map( A => input_fcs(0), B => input_fcs(5), Q => output_wip_7)
                           ;
   U24 : EO1 port map( A => input_fcs(2), B => input_fcs(0), Q => output_wip_23
                           );
   U25 : EO1 port map( A => input_fcs(0), B => input_fcs(4), Q => output_wip_31
                           );
   U26 : EO1 port map( A => input_fcs(3), B => input_fcs(0), Q => output_wip_4)
                           ;

end SYN_behavior;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity gf_xor_2x is

   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip : 
         out std_logic_vector (0 to 31));

end gf_xor_2x;

architecture SYN_behavior of gf_xor_2x is

   component EO1
      port( A, B : in std_logic;  Q : out std_logic);
   end component;

begin
   
   U7 : EO1 port map( A => input_wip(16), B => input_fcs(6), Q => 
                           output_wip(16));
   U8 : EO1 port map( A => input_wip(14), B => input_fcs(6), Q => 
                           output_wip(14));
   U9 : EO1 port map( A => input_wip(21), B => input_fcs(6), Q => 
                           output_wip(21));
   U10 : EO1 port map( A => input_wip(29), B => input_fcs(6), Q => 
                           output_wip(29));
   U11 : EO1 port map( A => input_wip(10), B => input_fcs(6), Q => 
                           output_wip(10));
   U12 : EO1 port map( A => input_wip(24), B => input_fcs(7), Q => 
                           output_wip(24));
   U13 : EO1 port map( A => input_wip(1), B => input_fcs(7), Q => output_wip(1)
                           );
   U14 : EO1 port map( A => input_wip(9), B => input_fcs(4), Q => output_wip(9)
                           );
   U15 : EO1 port map( A => input_wip(12), B => input_fcs(7), Q => 
                           output_wip(12));
   U16 : EO1 port map( A => input_wip(13), B => input_fcs(5), Q => 
                           output_wip(13));
   U17 : EO1 port map( A => input_wip(17), B => input_fcs(4), Q => 
                           output_wip(17));
   U18 : EO1 port map( A => input_wip(18), B => input_fcs(5), Q => 
                           output_wip(18));
   U19 : EO1 port map( A => input_wip(23), B => input_fcs(5), Q => 
                           output_wip(23));
   U20 : EO1 port map( A => input_wip(25), B => input_fcs(7), Q => 
                           output_wip(25));
   U21 : EO1 port map( A => input_wip(30), B => input_fcs(4), Q => 
                           output_wip(30));
   U22 : EO1 port map( A => input_wip(0), B => input_fcs(6), Q => output_wip(0)
                           );
   U23 : EO1 port map( A => input_wip(31), B => input_fcs(6), Q => 
                           output_wip(31));
   U24 : EO1 port map( A => input_wip(6), B => input_fcs(7), Q => output_wip(6)
                           );
   U25 : EO1 port map( A => input_wip(11), B => input_fcs(7), Q => 
                           output_wip(11));
   U26 : EO1 port map( A => input_wip(8), B => input_fcs(6), Q => output_wip(8)
                           );
   U27 : EO1 port map( A => input_wip(3), B => input_fcs(9), Q => output_wip(3)
                           );
   U28 : EO1 port map( A => input_wip(4), B => input_fcs(10), Q => 
                           output_wip(4));
   U29 : EO1 port map( A => input_wip(5), B => input_fcs(11), Q => 
                           output_wip(5));
   U30 : EO1 port map( A => input_wip(20), B => input_fcs(3), Q => 
                           output_wip(20));
   U31 : EO1 port map( A => input_wip(7), B => input_fcs(8), Q => output_wip(7)
                           );
   U32 : EO1 port map( A => input_wip(2), B => input_fcs(8), Q => output_wip(2)
                           );
   U33 : EO1 port map( A => input_wip(26), B => input_fcs(8), Q => 
                           output_wip(26));
   U34 : EO1 port map( A => input_wip(28), B => input_fcs(5), Q => 
                           output_wip(28));
   U35 : EO1 port map( A => input_wip(15), B => input_fcs(7), Q => 
                           output_wip(15));
   U36 : EO1 port map( A => input_wip(27), B => input_fcs(4), Q => 
                           output_wip(27));
   U37 : EO1 port map( A => input_wip(22), B => input_fcs(4), Q => 
                           output_wip(22));
   U38 : EO1 port map( A => input_wip(19), B => input_fcs(3), Q => 
                           output_wip(19));

end SYN_behavior;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity gf_xor_3x is

   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip : 
         out std_logic_vector (0 to 31));

end gf_xor_3x;

architecture SYN_behavior of gf_xor_3x is

   component EO1
      port( A, B : in std_logic;  Q : out std_logic);
   end component;

begin
   
   U7 : EO1 port map( A => input_wip(25), B => input_fcs(8), Q => 
                           output_wip(25));
   U8 : EO1 port map( A => input_wip(12), B => input_fcs(8), Q => 
                           output_wip(12));
   U9 : EO1 port map( A => input_wip(13), B => input_fcs(8), Q => 
                           output_wip(13));
   U10 : EO1 port map( A => input_wip(18), B => input_fcs(8), Q => 
                           output_wip(18));
   U11 : EO1 port map( A => input_wip(24), B => input_fcs(8), Q => 
                           output_wip(24));
   U12 : EO1 port map( A => input_wip(23), B => input_fcs(7), Q => 
                           output_wip(23));
   U13 : EO1 port map( A => input_wip(27), B => input_fcs(7), Q => 
                           output_wip(27));
   U14 : EO1 port map( A => input_wip(16), B => input_fcs(7), Q => 
                           output_wip(16));
   U15 : EO1 port map( A => input_wip(17), B => input_fcs(7), Q => 
                           output_wip(17));
   U16 : EO1 port map( A => input_wip(29), B => input_fcs(7), Q => 
                           output_wip(29));
   U17 : EO1 port map( A => input_wip(22), B => input_fcs(6), Q => 
                           output_wip(22));
   U18 : EO1 port map( A => input_wip(28), B => input_fcs(6), Q => 
                           output_wip(28));
   U19 : EO1 port map( A => input_wip(19), B => input_fcs(6), Q => 
                           output_wip(19));
   U20 : EO1 port map( A => input_wip(20), B => input_fcs(6), Q => 
                           output_wip(20));
   U21 : EO1 port map( A => input_wip(30), B => input_fcs(6), Q => 
                           output_wip(30));
   U22 : EO1 port map( A => input_wip(7), B => input_fcs(13), Q => 
                           output_wip(7));
   U23 : EO1 port map( A => input_wip(11), B => input_fcs(11), Q => 
                           output_wip(11));
   U24 : EO1 port map( A => input_fcs(11), B => input_wip(4), Q => 
                           output_wip(4));
   U25 : EO1 port map( A => input_wip(6), B => input_fcs(12), Q => 
                           output_wip(6));
   U26 : EO1 port map( A => input_fcs(12), B => input_wip(5), Q => 
                           output_wip(5));
   U27 : EO1 port map( A => input_wip(21), B => input_fcs(10), Q => 
                           output_wip(21));
   U28 : EO1 port map( A => input_wip(15), B => input_fcs(10), Q => 
                           output_wip(15));
   U29 : EO1 port map( A => input_wip(10), B => input_fcs(10), Q => 
                           output_wip(10));
   U30 : EO1 port map( A => input_fcs(10), B => input_wip(3), Q => 
                           output_wip(3));
   U31 : EO1 port map( A => input_wip(31), B => input_fcs(9), Q => 
                           output_wip(31));
   U32 : EO1 port map( A => input_wip(14), B => input_fcs(9), Q => 
                           output_wip(14));
   U33 : EO1 port map( A => input_wip(8), B => input_fcs(9), Q => output_wip(8)
                           );
   U34 : EO1 port map( A => input_fcs(9), B => input_wip(2), Q => output_wip(2)
                           );
   U35 : EO1 port map( A => input_wip(26), B => input_fcs(9), Q => 
                           output_wip(26));
   U36 : EO1 port map( A => input_fcs(8), B => input_wip(1), Q => output_wip(1)
                           );
   U37 : EO1 port map( A => input_fcs(7), B => input_wip(0), Q => output_wip(0)
                           );
   U38 : EO1 port map( A => input_fcs(6), B => input_wip(9), Q => output_wip(9)
                           );

end SYN_behavior;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity gf_xor_4x is

   port( input_wip, input_fcs : in std_logic_vector (0 to 31);  output_wip : 
         out std_logic_vector (0 to 31));

end gf_xor_4x;

architecture SYN_behavior of gf_xor_4x is

   component EO1
      port( A, B : in std_logic;  Q : out std_logic);
   end component;

begin
   
   U7 : EO1 port map( A => input_wip(26), B => input_fcs(10), Q => 
                           output_wip(26));
   U8 : EO1 port map( A => input_wip(0), B => input_fcs(10), Q => output_wip(0)
                           );
   U9 : EO1 port map( A => input_wip(1), B => input_fcs(11), Q => output_wip(1)
                           );
   U10 : EO1 port map( A => input_wip(7), B => input_fcs(14), Q => 
                           output_wip(7));
   U11 : EO1 port map( A => input_wip(12), B => input_fcs(12), Q => 
                           output_wip(12));
   U12 : EO1 port map( A => input_wip(14), B => input_fcs(10), Q => 
                           output_wip(14));
   U13 : EO1 port map( A => input_wip(16), B => input_fcs(8), Q => 
                           output_wip(16));
   U14 : EO1 port map( A => input_wip(18), B => input_fcs(9), Q => 
                           output_wip(18));
   U15 : EO1 port map( A => input_wip(19), B => input_fcs(9), Q => 
                           output_wip(19));
   U16 : EO1 port map( A => input_wip(25), B => input_fcs(9