crc_top_syn.vhd

来自「一个verilog实现的crc校验」· VHDL 代码 · 共 1,346 行 · 第 1/5 页

architecture SYN_behavior_0 of input_phi1_register_0 is

   component DFA2
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   component IN1
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   component IN3
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   signal n76, n80, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
      n123, n124, n125, n126, n127, n128 : std_logic;

begin
   
   output_reg_15 : DFA2 port map( C => phi1, D => input(0), Q => output(0), QN 
                           => n113, RN => n80);
   output_reg_14 : DFA2 port map( C => phi1, D => input(1), Q => output(1), QN 
                           => n114, RN => n80);
   output_reg_13 : DFA2 port map( C => phi1, D => input(2), Q => output(2), QN 
                           => n115, RN => n80);
   output_reg_12 : DFA2 port map( C => phi1, D => input(3), Q => output(3), QN 
                           => n116, RN => n80);
   output_reg_11 : DFA2 port map( C => phi1, D => input(4), Q => output(4), QN 
                           => n117, RN => n80);
   output_reg_10 : DFA2 port map( C => phi1, D => input(5), Q => output(5), QN 
                           => n118, RN => n80);
   output_reg_9 : DFA2 port map( C => phi1, D => input(6), Q => output(6), QN 
                           => n119, RN => n80);
   output_reg_8 : DFA2 port map( C => phi1, D => input(7), Q => output(7), QN 
                           => n120, RN => n80);
   output_reg_7 : DFA2 port map( C => phi1, D => input(8), Q => output(8), QN 
                           => n121, RN => n80);
   output_reg_6 : DFA2 port map( C => phi1, D => input(9), Q => output(9), QN 
                           => n122, RN => n80);
   output_reg_5 : DFA2 port map( C => phi1, D => input(10), Q => output(10), QN
                           => n123, RN => n80);
   output_reg_4 : DFA2 port map( C => phi1, D => input(11), Q => output(11), QN
                           => n124, RN => n80);
   output_reg_3 : DFA2 port map( C => phi1, D => input(12), Q => output(12), QN
                           => n125, RN => n80);
   output_reg_2 : DFA2 port map( C => phi1, D => input(13), Q => output(13), QN
                           => n126, RN => n80);
   output_reg_1 : DFA2 port map( C => phi1, D => input(14), Q => output(14), QN
                           => n127, RN => n80);
   output_reg_0 : DFA2 port map( C => phi1, D => input(15), Q => output(15), QN
                           => n128, RN => n80);
   U48 : IN1 port map( A => reset, Q => n76);
   U49 : IN3 port map( A => n76, Q => n80);

end SYN_behavior_0;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_phi1_register_1 is

   port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);  
         output : out std_logic_vector (0 to 15));

end input_phi1_register_1;

architecture SYN_behavior_1 of input_phi1_register_1 is

   component DFA2
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   signal n107, n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, 
      n118, n119, n120, n121, n122 : std_logic;

begin
   
   output_reg_15 : DFA2 port map( C => phi1, D => input(0), Q => output(0), QN 
                           => n107, RN => reset);
   output_reg_14 : DFA2 port map( C => phi1, D => input(1), Q => output(1), QN 
                           => n108, RN => reset);
   output_reg_13 : DFA2 port map( C => phi1, D => input(2), Q => output(2), QN 
                           => n109, RN => reset);
   output_reg_12 : DFA2 port map( C => phi1, D => input(3), Q => output(3), QN 
                           => n110, RN => reset);
   output_reg_11 : DFA2 port map( C => phi1, D => input(4), Q => output(4), QN 
                           => n111, RN => reset);
   output_reg_10 : DFA2 port map( C => phi1, D => input(5), Q => output(5), QN 
                           => n112, RN => reset);
   output_reg_9 : DFA2 port map( C => phi1, D => input(6), Q => output(6), QN 
                           => n113, RN => reset);
   output_reg_8 : DFA2 port map( C => phi1, D => input(7), Q => output(7), QN 
                           => n114, RN => reset);
   output_reg_7 : DFA2 port map( C => phi1, D => input(8), Q => output(8), QN 
                           => n115, RN => reset);
   output_reg_6 : DFA2 port map( C => phi1, D => input(9), Q => output(9), QN 
                           => n116, RN => reset);
   output_reg_5 : DFA2 port map( C => phi1, D => input(10), Q => output(10), QN
                           => n117, RN => reset);
   output_reg_4 : DFA2 port map( C => phi1, D => input(11), Q => output(11), QN
                           => n118, RN => reset);
   output_reg_3 : DFA2 port map( C => phi1, D => input(12), Q => output(12), QN
                           => n119, RN => reset);
   output_reg_2 : DFA2 port map( C => phi1, D => input(13), Q => output(13), QN
                           => n120, RN => reset);
   output_reg_1 : DFA2 port map( C => phi1, D => input(14), Q => output(14), QN
                           => n121, RN => reset);
   output_reg_0 : DFA2 port map( C => phi1, D => input(15), Q => output(15), QN
                           => n122, RN => reset);

end SYN_behavior_1;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_phi1_register_2 is

   port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);  
         output : out std_logic_vector (0 to 15));

end input_phi1_register_2;

architecture SYN_behavior_2 of input_phi1_register_2 is

   component DFA2
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   component IN1
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   component IN3
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   signal n84, n86, n119, n120, n121, n122, n123, n124, n125, n126, n127, n128,
      n129, n130, n131, n132, n133, n134 : std_logic;

begin
   
   output_reg_15 : DFA2 port map( C => phi1, D => input(0), Q => output(0), QN 
                           => n119, RN => n86);
   output_reg_14 : DFA2 port map( C => phi1, D => input(1), Q => output(1), QN 
                           => n120, RN => n86);
   output_reg_13 : DFA2 port map( C => phi1, D => input(2), Q => output(2), QN 
                           => n121, RN => n86);
   output_reg_12 : DFA2 port map( C => phi1, D => input(3), Q => output(3), QN 
                           => n122, RN => n86);
   output_reg_11 : DFA2 port map( C => phi1, D => input(4), Q => output(4), QN 
                           => n123, RN => n86);
   output_reg_10 : DFA2 port map( C => phi1, D => input(5), Q => output(5), QN 
                           => n124, RN => n86);
   output_reg_9 : DFA2 port map( C => phi1, D => input(6), Q => output(6), QN 
                           => n125, RN => n86);
   output_reg_8 : DFA2 port map( C => phi1, D => input(7), Q => output(7), QN 
                           => n126, RN => n86);
   output_reg_7 : DFA2 port map( C => phi1, D => input(8), Q => output(8), QN 
                           => n127, RN => n86);
   output_reg_6 : DFA2 port map( C => phi1, D => input(9), Q => output(9), QN 
                           => n128, RN => n86);
   output_reg_5 : DFA2 port map( C => phi1, D => input(10), Q => output(10), QN
                           => n129, RN => n86);
   output_reg_4 : DFA2 port map( C => phi1, D => input(11), Q => output(11), QN
                           => n130, RN => n86);
   output_reg_3 : DFA2 port map( C => phi1, D => input(12), Q => output(12), QN
                           => n131, RN => n86);
   output_reg_2 : DFA2 port map( C => phi1, D => input(13), Q => output(13), QN
                           => n132, RN => n86);
   output_reg_1 : DFA2 port map( C => phi1, D => input(14), Q => output(14), QN
                           => n133, RN => n86);
   output_reg_0 : DFA2 port map( C => phi1, D => input(15), Q => output(15), QN
                           => n134, RN => n86);
   U48 : IN1 port map( A => reset, Q => n84);
   U49 : IN3 port map( A => n84, Q => n86);

end SYN_behavior_2;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_phi1_register_3 is

   port( reset, phi1 : in std_logic;  input : in std_logic_vector (0 to 15);  
         output : out std_logic_vector (0 to 15));

end input_phi1_register_3;

architecture SYN_behavior_3 of input_phi1_register_3 is

   component IN3
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   component IN1
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   component DFA2
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;
   
   component IN4
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   signal n88, n90, n92, n98, n100, n102, n104, n106, n111, n115, n119, n123, 
      n127, n131, n135, n139, n157, n159, n209, n210, n211, n212, n213, n214, 
      n215, n216, n217, n218, n219, n220, n221, n222, n223, n224 : std_logic;

begin
   
   U48 : IN3 port map( A => n92, Q => output(9));
   U49 : IN3 port map( A => n98, Q => output(5));
   U50 : IN3 port map( A => n100, Q => output(15));
   U51 : IN3 port map( A => n102, Q => output(1));
   U52 : IN3 port map( A => n104, Q => output(2));
   U53 : IN3 port map( A => n106, Q => output(12));
   U54 : IN1 port map( A => reset, Q => n88);
   U55 : IN3 port map( A => n88, Q => n90);
   output_reg_6 : DFA2 port map( C => phi1, D => input(9), Q => n209, QN => n92
                           , RN => n90);
   output_reg_10 : DFA2 port map( C => phi1, D => input(5), Q => n210, QN => 
                           n98, RN => n90);
   output_reg_0 : DFA2 port map( C => phi1, D => input(15), Q => n211, QN => 
                           n100, RN => n90);
   output_reg_14 : DFA2 port map( C => phi1, D => input(1), Q => n212, QN => 
                           n102, RN => n90);
   output_reg_13 : DFA2 port map( C => phi1, D => input(2), Q => n213, QN => 
                           n104, RN => n90);
   output_reg_3 : DFA2 port map( C => phi1, D => input(12), Q => n214, QN => 
                           n106, RN => n90);
   U56 : IN4 port map( A => n111, Q => output(0));
   output_reg_15 : DFA2 port map( C => phi1, D => input(0), Q => n215, QN => 
                           n111, RN => n90);
   U57 : IN4 port map( A => n115, Q => output(3));
   output_reg_12 : DFA2 port map( C => phi1, D => input(3), Q => n216, QN => 
                           n115, RN => n90);
   U58 : IN4 port map( A => n119, Q => output(11));
   output_reg_4 : DFA2 port map( C => phi1, D => input(11), Q => n217, QN => 
                           n119, RN => n90);
   U59 : IN4 port map( A => n123, Q => output(10));
   output_reg_5 : DFA2 port map( C => phi1, D => input(10), Q => n218, QN => 
                           n123, RN => n90);
   U60 : IN4 port map( A => n127, Q => output(13));
   output_reg_2 : DFA2 port map( C => phi1, D => input(13), Q => n219, QN => 
                           n127, RN => n90);
   U61 : IN4 port map( A => n131, Q => output(6));
   output_reg_9 : DFA2 port map( C => phi1, D => input(6), Q => n220, QN => 
                           n131, RN => n90);
   U62 : IN4 port map( A => n135, Q => output(4));