crc_top_syn.vhd

一个verilog实现的crc校验

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity CRC_top is

   port( phi1, phi2, reset : in std_logic;  input : in std_logic_vector (0 to 
         15);  fcs_out : out std_logic_vector (0 to 31));

end CRC_top;

architecture SYN_structural of CRC_top is

   component ff_reset
      port( phi2, reset_glitch : in std_logic;  reset_clean : out std_logic);
   end component;
   
   component input_wait
      port( phi1, phi2, reset : in std_logic;  input : in std_logic_vector (0 
            to 15);  output : out std_logic_vector (0 to 15));
   end component;
   
   component gf_multiplier
      port( reset, phi1, phi2 : in std_logic;  input : in std_logic_vector (0 
            to 31);  output_fcs, output_xor : out std_logic_vector (0 to 15));
   end component;
   
   component big_xor
      port( reset, phi2 : in std_logic;  input_input, fcs_input, gf_input : in 
            std_logic_vector (0 to 15);  output : out std_logic_vector (0 to 
            31));
   end component;
   
   signal wait_intermediate_10, xor_intermediate_0, fcs_out_15, fcs_out_4, 
      fcs_intermediate_10, fcs_intermediate_8, fcs_out_29, xor_intermediate_9, 
      wait_intermediate_2, fcs_intermediate_6, fcs_intermediate_1, fcs_out_27, 
      fcs_out_20, wait_intermediate_5, reset_intermediate, xor_intermediate_11,
      fcs_out_3, wait_intermediate_15, wait_intermediate_14, 
      wait_intermediate_13, wait_intermediate_11, wait_intermediate_4, 
      xor_intermediate_7, fcs_out_12, wait_intermediate_3, fcs_intermediate_7, 
      fcs_out_26, fcs_out_13, xor_intermediate_6, fcs_out_2, 
      xor_intermediate_10, fcs_intermediate_9, fcs_out_28, fcs_out_5, 
      fcs_intermediate_0, xor_intermediate_1, fcs_out_14, fcs_out_21, 
      xor_intermediate_8, wait_intermediate_8, fcs_intermediate_11, 
      xor_intermediate_15, xor_intermediate_3, fcs_out_31, fcs_out_16, 
      fcs_out_7, fcs_intermediate_13, wait_intermediate_6, wait_intermediate_1,
      fcs_intermediate_5, fcs_intermediate_2, fcs_out_24, fcs_out_23, fcs_out_9
      , fcs_intermediate_14, fcs_out_18, xor_intermediate_12, 
      fcs_intermediate_15, xor_intermediate_4, fcs_out_11, fcs_out_0, 
      wait_intermediate_7, fcs_out_19, fcs_intermediate_4, fcs_out_8, 
      fcs_out_25, xor_intermediate_13, xor_intermediate_5, fcs_out_10, 
      fcs_out_1, xor_intermediate_14, wait_intermediate_12, wait_intermediate_9
      , wait_intermediate_0, fcs_intermediate_3, xor_intermediate_2, fcs_out_30
      , fcs_out_6, fcs_out_17, fcs_out_22, fcs_intermediate_12 : std_logic;

begin
   fcs_out <= ( fcs_out_31, fcs_out_30, fcs_out_29, fcs_out_28, fcs_out_27, 
      fcs_out_26, fcs_out_25, fcs_out_24, fcs_out_23, fcs_out_22, fcs_out_21, 
      fcs_out_20, fcs_out_19, fcs_out_18, fcs_out_17, fcs_out_16, fcs_out_15, 
      fcs_out_14, fcs_out_13, fcs_out_12, fcs_out_11, fcs_out_10, fcs_out_9, 
      fcs_out_8, fcs_out_7, fcs_out_6, fcs_out_5, fcs_out_4, fcs_out_3, 
      fcs_out_2, fcs_out_1, fcs_out_0 );
   
   ff_reset_1 : ff_reset port map( phi2 => phi2, reset_glitch => reset, 
                           reset_clean => reset_intermediate);
   input_wait_1 : input_wait port map( phi1 => phi1, phi2 => phi2, reset => 
                           reset_intermediate, input(0) => input(0), input(1) 
                           => input(1), input(2) => input(2), input(3) => 
                           input(3), input(4) => input(4), input(5) => input(5)
                           , input(6) => input(6), input(7) => input(7), 
                           input(8) => input(8), input(9) => input(9), 
                           input(10) => input(10), input(11) => input(11), 
                           input(12) => input(12), input(13) => input(13), 
                           input(14) => input(14), input(15) => input(15), 
                           output(0) => wait_intermediate_15, output(1) => 
                           wait_intermediate_14, output(2) => 
                           wait_intermediate_13, output(3) => 
                           wait_intermediate_12, output(4) => 
                           wait_intermediate_11, output(5) => 
                           wait_intermediate_10, output(6) => 
                           wait_intermediate_9, output(7) => 
                           wait_intermediate_8, output(8) => 
                           wait_intermediate_7, output(9) => 
                           wait_intermediate_6, output(10) => 
                           wait_intermediate_5, output(11) => 
                           wait_intermediate_4, output(12) => 
                           wait_intermediate_3, output(13) => 
                           wait_intermediate_2, output(14) => 
                           wait_intermediate_1, output(15) => 
                           wait_intermediate_0);
   gf_multiplier_1 : gf_multiplier port map( reset => reset_intermediate, phi1 
                           => phi1, phi2 => phi2, input(0) => fcs_out_31, 
                           input(1) => fcs_out_30, input(2) => fcs_out_29, 
                           input(3) => fcs_out_28, input(4) => fcs_out_27, 
                           input(5) => fcs_out_26, input(6) => fcs_out_25, 
                           input(7) => fcs_out_24, input(8) => fcs_out_23, 
                           input(9) => fcs_out_22, input(10) => fcs_out_21, 
                           input(11) => fcs_out_20, input(12) => fcs_out_19, 
                           input(13) => fcs_out_18, input(14) => fcs_out_17, 
                           input(15) => fcs_out_16, input(16) => fcs_out_15, 
                           input(17) => fcs_out_14, input(18) => fcs_out_13, 
                           input(19) => fcs_out_12, input(20) => fcs_out_11, 
                           input(21) => fcs_out_10, input(22) => fcs_out_9, 
                           input(23) => fcs_out_8, input(24) => fcs_out_7, 
                           input(25) => fcs_out_6, input(26) => fcs_out_5, 
                           input(27) => fcs_out_4, input(28) => fcs_out_3, 
                           input(29) => fcs_out_2, input(30) => fcs_out_1, 
                           input(31) => fcs_out_0, output_fcs(0) => 
                           fcs_intermediate_15, output_fcs(1) => 
                           fcs_intermediate_14, output_fcs(2) => 
                           fcs_intermediate_13, output_fcs(3) => 
                           fcs_intermediate_12, output_fcs(4) => 
                           fcs_intermediate_11, output_fcs(5) => 
                           fcs_intermediate_10, output_fcs(6) => 
                           fcs_intermediate_9, output_fcs(7) => 
                           fcs_intermediate_8, output_fcs(8) => 
                           fcs_intermediate_7, output_fcs(9) => 
                           fcs_intermediate_6, output_fcs(10) => 
                           fcs_intermediate_5, output_fcs(11) => 
                           fcs_intermediate_4, output_fcs(12) => 
                           fcs_intermediate_3, output_fcs(13) => 
                           fcs_intermediate_2, output_fcs(14) => 
                           fcs_intermediate_1, output_fcs(15) => 
                           fcs_intermediate_0, output_xor(0) => 
                           xor_intermediate_15, output_xor(1) => 
                           xor_intermediate_14, output_xor(2) => 
                           xor_intermediate_13, output_xor(3) => 
                           xor_intermediate_12, output_xor(4) => 
                           xor_intermediate_11, output_xor(5) => 
                           xor_intermediate_10, output_xor(6) => 
                           xor_intermediate_9, output_xor(7) => 
                           xor_intermediate_8, output_xor(8) => 
                           xor_intermediate_7, output_xor(9) => 
                           xor_intermediate_6, output_xor(10) => 
                           xor_intermediate_5, output_xor(11) => 
                           xor_intermediate_4, output_xor(12) => 
                           xor_intermediate_3, output_xor(13) => 
                           xor_intermediate_2, output_xor(14) => 
                           xor_intermediate_1, output_xor(15) => 
                           xor_intermediate_0);
   big_xor_1 : big_xor port map( reset => reset_intermediate, phi2 => phi2, 
                           input_input(0) => wait_intermediate_15, 
                           input_input(1) => wait_intermediate_14, 
                           input_input(2) => wait_intermediate_13, 
                           input_input(3) => wait_intermediate_12, 
                           input_input(4) => wait_intermediate_11, 
                           input_input(5) => wait_intermediate_10, 
                           input_input(6) => wait_intermediate_9, 
                           input_input(7) => wait_intermediate_8, 
                           input_input(8) => wait_intermediate_7, 
                           input_input(9) => wait_intermediate_6, 
                           input_input(10) => wait_intermediate_5, 
                           input_input(11) => wait_intermediate_4, 
                           input_input(12) => wait_intermediate_3, 
                           input_input(13) => wait_intermediate_2, 
                           input_input(14) => wait_intermediate_1, 
                           input_input(15) => wait_intermediate_0, fcs_input(0)
                           => fcs_intermediate_15, fcs_input(1) => 
                           fcs_intermediate_14, fcs_input(2) => 
                           fcs_intermediate_13, fcs_input(3) => 
                           fcs_intermediate_12, fcs_input(4) => 
                           fcs_intermediate_11, fcs_input(5) => 
                           fcs_intermediate_10, fcs_input(6) => 
                           fcs_intermediate_9, fcs_input(7) => 
                           fcs_intermediate_8, fcs_input(8) => 
                           fcs_intermediate_7, fcs_input(9) => 
                           fcs_intermediate_6, fcs_input(10) => 
                           fcs_intermediate_5, fcs_input(11) => 
                           fcs_intermediate_4, fcs_input(12) => 
                           fcs_intermediate_3, fcs_input(13) => 
                           fcs_intermediate_2, fcs_input(14) => 
                           fcs_intermediate_1, fcs_input(15) => 
                           fcs_intermediate_0, gf_input(0) => 
                           xor_intermediate_15, gf_input(1) => 
                           xor_intermediate_14, gf_input(2) => 
                           xor_intermediate_13, gf_input(3) => 
                           xor_intermediate_12, gf_input(4) => 
                           xor_intermediate_11, gf_input(5) => 
                           xor_intermediate_10, gf_input(6) => 
                           xor_intermediate_9, gf_input(7) => 
                           xor_intermediate_8, gf_input(8) => 
                           xor_intermediate_7, gf_input(9) => 
                           xor_intermediate_6, gf_input(10) => 
                           xor_intermediate_5, gf_input(11) => 
                           xor_intermediate_4, gf_input(12) => 
                           xor_intermediate_3, gf_input(13) => 
                           xor_intermediate_2, gf_input(14) => 
                           xor_intermediate_1, gf_input(15) => 
                           xor_intermediate_0, output(0) => fcs_out_31, 
                           output(1) => fcs_out_30, output(2) => fcs_out_29, 
                           output(3) => fcs_out_28, output(4) => fcs_out_27, 
                           output(5) => fcs_out_26, output(6) => fcs_out_25, 
                           output(7) => fcs_out_24, output(8) => fcs_out_23, 
                           output(9) => fcs_out_22, output(10) => fcs_out_21, 
                           output(11) => fcs_out_20, output(12) => fcs_out_19, 
                           output(13) => fcs_out_18, output(14) => fcs_out_17, 
                           output(15) => fcs_out_16, output(16) => fcs_out_15, 
                           output(17) => fcs_out_14, output(18) => fcs_out_13, 
                           output(19) => fcs_out_12, output(20) => fcs_out_11, 
                           output(21) => fcs_out_10, output(22) => fcs_out_9, 
                           output(23) => fcs_out_8, output(24) => fcs_out_7, 
                           output(25) => fcs_out_6, output(26) => fcs_out_5, 
                           output(27) => fcs_out_4, output(28) => fcs_out_3, 
                           output(29) => fcs_out_2, output(30) => fcs_out_1, 
                           output(31) => fcs_out_0);

end SYN_structural;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity ff_reset is

   port( phi2, reset_glitch : in std_logic;  reset_clean : out std_logic);

end ff_reset;

architecture SYN_behavior of ff_reset is

   component IN8
      port( A : in std_logic;  Q : out std_logic);
   end component;
   
   component DF8
      port( C, D : in std_logic;  Q, QN : out std_logic);
   end component;
   
   signal n15, n20 : std_logic;

begin
   
   U9 : IN8 port map( A => n15, Q => reset_clean);
   reset_clean_reg : DF8 port map( C => phi2, D => reset_glitch, Q => n20, QN 
                           => n15);

end SYN_behavior;

library IEEE;
library csx_HRDLIB;
library csx_IOLIB_3M;

use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use csx_HRDLIB.Vcomponents.all;
use csx_IOLIB_3M.Vcomponents.all;

entity input_phi2_register_0 is

   port( reset, phi2 : in std_logic;  input : in std_logic_vector (0 to 15);  
         output : out std_logic_vector (0 to 15));

end input_phi2_register_0;

architecture SYN_behavior_0 of input_phi2_register_0 is

   component DFA2
      port( C, D : in std_logic;  Q, QN : out std_logic;  RN : in std_logic);
   end component;