d1_dct.v

采用verilog hdl 语言实现整形dct算法

module dct(clk,rst_n,
		   data_in0,data_in1,data_in2,data_in3,
		   data_out0,data_out1,data_out2,data_out3,
		   data_in_en,data_out_en
		  );
		  		
input            clk,rst_n                               ;
input   [15:0 ]  data_in0,data_in1,data_in2,data_in3     ;
input            data_in_en                              ;

output  [15:0 ]  data_out0,data_out1,data_out2,data_out3 ;
output           data_out_en                             ;

reg              data_out_en                             ;
reg              en_Reg                                  ;
reg     [15:0 ]  fs03,fs12,fd03,fd12                     ;
reg     [15:0 ]  data_out0,data_out1,data_out2,data_out3 ;
reg     [3 :0 ]  cnt                                     ;

wire    [15:0 ]  fd03_mux2                               ;
wire    [15:0 ]  fd12_mux2                               ;

always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		cnt <= 0 ;
	else
		begin
			if( data_in_en )
				begin
					if( !en_Reg )
						cnt <= 4'b0001 ;
					else
						begin
							if( (cnt <= 4'b1110)&&(cnt != 4'b0000) )
								cnt <= cnt + 4'b0001 ;
							else
								cnt <= cnt ;
						end
				end
			else
				begin
					if( (cnt <= 4'b1110)&&(cnt != 4'b0000) )
						cnt <= cnt + 4'b0001 ;
					else
						cnt <= cnt ;
				end
		end
		
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		data_out_en <= 0 ;
	else
		begin
			if( cnt == 4'b0001 )
				data_out_en <= 1 ;
			if( cnt == 4'b0101 )	
				data_out_en <= 0 ;

		end
		
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		en_Reg <= 0 ;
	else
		en_Reg <= data_in_en ;
		
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		begin
			fs03 <= 0 ;
			fs12 <= 0 ;
			fd12 <= 0 ;
			fd03 <= 0 ;
		end
	else
		begin
			fs03 <= data_in0 + data_in3 ;
			fs12 <= data_in1 + data_in2 ;
			fd12 <= data_in1 - data_in2 ;
			fd03 <= data_in0 - data_in3 ;
		end	

assign  fd03_mux2 = {fd03[14:0],1'b0} ;
assign  fd12_mux2 = {fd12[14:0],1'b0} ;
			
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		begin
			data_out0 <= 0 ;
			data_out1 <= 0 ;
			data_out2 <= 0 ;
			data_out3 <= 0 ;
		end
	else
		begin
			if( en_Reg )
				begin
					data_out0 <= fs03      + fs12      ;
					data_out1 <= fd03_mux2 + fd12      ;
					data_out2 <= fs03      - fs12      ;
					data_out3 <= fd03      - fd12_mux2 ;  
				end
			else
				begin
					data_out0 <= 0 ;
					data_out1 <= 0 ;
					data_out2 <= 0 ;
					data_out3 <= 0 ;
				end
		end
endmodule

module dct_test;
		
reg            clk,rst_n                               ;
reg  [15:0 ]   data_in0,data_in1,data_in2,data_in3     ;
reg            data_in_en                              ;

wire [15:0 ]   data_out0,data_out1,data_out2,data_out3 ;
wire           data_out_en                             ;

initial
	begin
		clk = 0 ;
		rst_n = 1 ;
		data_in_en = 0 ;
		#100 rst_n = 0 ;
		#100 rst_n = 1 ;
		#200 data_in_en = 1 ;
		data_in0 = 16;
		data_in1 = 16;
		data_in2 = 16;
		data_in3 = 16;
		#200 data_in0 = 16;
		data_in1 = 16;
		data_in2 = 16;
		data_in3 = 16;
		#200 data_in0 = 16;
		data_in1 = 16;
		data_in2 = 16;
		data_in3 = 16;
		#200 data_in0 = 16;
		data_in1 = 16;
		data_in2 = 16;
		data_in3 = 16;
		#200 data_in_en = 0 ;
		#2000 $stop ;
	end
	always #100 clk = ~clk ;
dct dct_tt(.clk(clk),.rst_n(rst_n),
		   .data_in0(data_in0),.data_in1(data_in1),
		   .data_in2(data_in2),.data_in3(data_in3),
		   .data_out0(data_out0),.data_out1(data_out1),
		   .data_out2(data_out2),.data_out3(data_out3),
		   .data_in_en(data_in_en),.data_out_en(data_out_en)
		  );
endmodule