d2_dct.v

采用verilog hdl 语言实现整形dct算法

module dct(clk,rst_n,
		   data_in0,data_in1,data_in2,data_in3,
		   data_out0,data_out1,data_out2,data_out3,
		   data_in_en,data_out_en
		  );
		
input            clk,rst_n                               ;
input   [15:0 ]  data_in0,data_in1,data_in2,data_in3     ;
input            data_in_en                              ;

output  [15:0 ]  data_out0,data_out1,data_out2,data_out3 ;
output           data_out_en                             ;

reg              data_out_en                             ;
reg              en_Reg                                  ;
reg              oe                                      ;
reg     [15:0 ]  fs03,fs12,fd03,fd12                     ;
reg     [15:0 ]  fd_out                         [3 :0 ]  ;
reg     [15:0 ]  dct_reg                        [15:0 ]  ;
reg     [15:0 ]  sd_in                          [3 :0 ]  ;
reg     [15:0 ]  ss03,ss12,sd03,sd12                     ;
reg     [15:0 ]  data_out0,data_out1,data_out2,data_out3 ;
reg     [3 :0 ]  cnt                                     ;

wire    [15:0 ]  fd03_mux2                               ;
wire    [15:0 ]  fd12_mux2                               ;
wire    [15:0 ]  sd03_mux2                               ;
wire    [15:0 ]  sd12_mux2                               ;  

always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		cnt <= 0 ;
	else
		begin
			if( data_in_en )
				begin
					if( !en_Reg )
						cnt <= 4'b0001 ;
					else
						begin
							if( (cnt <= 4'b1110)&&(cnt != 4'b0000) )
								cnt <= cnt + 4'b0001 ;
							else
								cnt <= cnt ;
						end
				end
			else
				begin
					if( (cnt <= 4'b1110)&&(cnt != 4'b0000) )
						cnt <= cnt + 4'b0001 ;
					else
						cnt <= cnt ;
				end
		end
		
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		oe <= 0 ;
	else
		begin
			if( cnt == 4'b0101 )
				oe <= ~oe ;
			else
				oe <= oe ;
		end

always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		data_out_en <= 0 ;
	else
		begin
			if( cnt == 4'b1000 )
				data_out_en <= 1 ;
			if( cnt == 4'b1100 )	
				data_out_en <= 0 ;
		end
		
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		en_Reg <= 0 ;
	else
		en_Reg <= data_in_en ;
				
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		begin
			fs03 <= 0 ;
			fs12 <= 0 ;
			fd12 <= 0 ;
			fd03 <= 0 ;
		end
	else
		begin
			fs03 <= data_in0 + data_in3 ;
			fs12 <= data_in1 + data_in2 ;
			fd12 <= data_in1 - data_in2 ;
			fd03 <= data_in0 - data_in3 ;
		end	

assign  fd03_mux2 = {fd03[14:0],1'b0} ;
assign  fd12_mux2 = {fd12[14:0],1'b0} ;
			
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		begin
			fd_out[0] <= 0 ;
			fd_out[1] <= 0 ;
			fd_out[2] <= 0 ;
			fd_out[3] <= 0 ;
		end
	else
		begin
			if( en_Reg )
				begin
					fd_out[0] <= fs03      + fs12      ;
					fd_out[1] <= fd03_mux2 + fd12      ;
					fd_out[2] <= fs03      - fs12      ;
					fd_out[3] <= fd03      - fd12_mux2 ;  
				end
			else
				begin
					fd_out[0] <= 0 ;
					fd_out[1] <= 0 ;
					fd_out[2] <= 0 ;
					fd_out[3] <= 0 ;
				end
		end
				
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		begin
			sd_in[0] <= 0 ;
			sd_in[1] <= 0 ;
			sd_in[2] <= 0 ;
			sd_in[3] <= 0 ;
			dct_reg[0] <= 0 ; dct_reg[1] <= 0 ; dct_reg[2] <= 0 ; dct_reg[3] <= 0 ;
			dct_reg[4] <= 0 ; dct_reg[5] <= 0 ; dct_reg[6] <= 0 ; dct_reg[7] <= 0 ;
			dct_reg[8] <= 0 ; dct_reg[9] <= 0 ; dct_reg[10]<= 0 ; dct_reg[11]<= 0 ;
			dct_reg[12]<= 0 ; dct_reg[13]<= 0 ; dct_reg[14]<= 0 ; dct_reg[15]<= 0 ;
		end
	else
		begin
			if ( oe )
				begin
					dct_reg[0] <= fd_out[0]  ; dct_reg[1] <= fd_out[1]  ; 
					dct_reg[2] <= fd_out[2]  ; dct_reg[3] <= fd_out[3]  ;
					
					dct_reg[4] <= dct_reg[0] ; dct_reg[5] <= dct_reg[1] ;
					dct_reg[6] <= dct_reg[2] ; dct_reg[7] <= dct_reg[3] ;
					
					dct_reg[8] <= dct_reg[4] ; dct_reg[9] <= dct_reg[5] ;
					dct_reg[10]<= dct_reg[6] ; dct_reg[11]<= dct_reg[7] ; 
					
					dct_reg[12]<= dct_reg[8] ; dct_reg[13]<= dct_reg[9] ;
					dct_reg[14]<= dct_reg[10]; dct_reg[15]<= dct_reg[11];
					
					sd_in[0]   <= dct_reg[12]; sd_in[1]   <= dct_reg[13];
					sd_in[2]   <= dct_reg[14]; sd_in[3]   <= dct_reg[15];
				end
			else
				begin
					dct_reg[3] <= fd_out[3]  ; dct_reg[7] <= fd_out[2]  ; 
					dct_reg[11]<= fd_out[1]  ; dct_reg[15]<= fd_out[0]  ; 
					                                                          
					dct_reg[2] <= dct_reg[3] ; dct_reg[6] <= dct_reg[7] ; 
					dct_reg[10]<= dct_reg[11]; dct_reg[14]<= dct_reg[15]; 
					                                                          
					dct_reg[1] <= dct_reg[2] ; dct_reg[5] <= dct_reg[6] ; 
					dct_reg[9] <= dct_reg[10]; dct_reg[13]<= dct_reg[14]; 
					
					dct_reg[0] <= dct_reg[1] ; dct_reg[4] <= dct_reg[5] ;
					dct_reg[8] <= dct_reg[9] ; dct_reg[12]<= dct_reg[13];
					
					sd_in[3]   <= dct_reg[0] ; sd_in[2]   <= dct_reg[4] ;
					sd_in[1]   <= dct_reg[8] ; sd_in[0]   <= dct_reg[12];
				end
		end	
			
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		begin
			ss03 <= 0 ;
			ss12 <= 0 ;
			sd12 <= 0 ;
			sd03 <= 0 ;
		end
	else
		begin
			ss03 <= sd_in[0] + sd_in[3] ;
			ss12 <= sd_in[1] + sd_in[2] ;
			sd12 <= sd_in[1] - sd_in[2] ;
			sd03 <= sd_in[0] - sd_in[3] ;
		end	

assign  sd03_mux2 = {sd03[14:0],1'b0} ;
assign  sd12_mux2 = {sd12[14:0],1'b0} ;
			
always @ ( posedge clk or negedge rst_n )
	if( !rst_n )
		begin
			data_out0 <= 0 ;
			data_out1 <= 0 ;
			data_out2 <= 0 ;
			data_out3 <= 0 ;
		end
	else
		begin
			data_out0 <= ss03      + ss12      ;
			data_out1 <= sd03_mux2 + sd12      ;
			data_out2 <= ss03      - ss12      ;
			data_out3 <= sd03      - sd12_mux2 ;
		end
endmodule

module dct_test;
		
reg            clk,rst_n                               ;
reg  [15:0 ]   data_in0,data_in1,data_in2,data_in3     ;
reg            data_in_en                              ;

wire [15:0 ]   data_out0,data_out1,data_out2,data_out3 ;
wire           data_out_en                             ;

initial
	begin
		clk = 0 ;
		rst_n = 1 ;
		data_in_en = 0 ;
		#100 rst_n = 0 ;
		#100 rst_n = 1 ;
		#200 data_in_en = 1 ;
		data_in0 = 16;
		data_in1 = 16;
		data_in2 = 16;
		data_in3 = 16;
		#200 data_in0 = 16;
		data_in1 = 16;
		data_in2 = 16;
		data_in3 = 16;
		#200 data_in0 = 16;
		data_in1 = 16;
		data_in2 = 16;
		data_in3 = 16;
		#200 data_in0 = 16;
		data_in1 = 16;
		data_in2 = 16;
		data_in3 = 16;
		#200 data_in_en = 0 ;
		#2000 $stop ;
	end
	always #100 clk = ~clk ;
dct dct_tt(.clk(clk),.rst_n(rst_n),
		   .data_in0(data_in0),.data_in1(data_in1),
		   .data_in2(data_in2),.data_in3(data_in3),
		   .data_out0(data_out0),.data_out1(data_out1),
		   .data_out2(data_out2),.data_out3(data_out3),
		   .data_in_en(data_in_en),.data_out_en(data_out_en)
		  );
endmodule