fftls.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

       signal st3dRegi : signed(DataWidth downto 0);
       signal st4dRegi : signed(DataWidth downto 0);
       signal st5dRegi : signed(DataWidth downto 0);
       
       signal st0cRegr : signed(DataWidth downto 0);
       signal st1cRegr : signed(DataWidth downto 0);
       signal st2cRegr : signed(DataWidth downto 0);
       signal st3cRegr : signed(DataWidth downto 0);
       
		 signal st0cRegi : signed(DataWidth downto 0);
       signal st1cRegi : signed(DataWidth downto 0);
       signal st2cRegi : signed(DataWidth downto 0);
       signal st3cRegi : signed(DataWidth downto 0);
       
		 
		 signal st4cReg : signed(DataWidth downto 0); 
		 
		 function scaleMul(d, c :signed) return signed is
				variable r : signed(d'length + c'length -1 downto 0); 
--				variable dd,dc,dr,mul, eps : real;
--				variable cr : signed(DataWidth -1 downto 0);
			begin
				r := d * c;
				r := r(r'left -1 downto 0) & '0';
				
				return r(r'left downto r'left - d'length +1);
			end function scaleMul;
       --signal st5cReg : slvCoeft;
    begin
        --  td.re := d.re + d.im * c.re;
		  --  td.im := d.im + td.re * c.im;
		  --  td.re := td.re + td.im * c.re;
		  
        st0:   process(clk) is
           begin
               if rising_edge(clk) then
                      st0dRegr <= conv_signed(DtGetRe(dti),DataWidth +1);
                      st0dRegi <= conv_signed(DtGetIm(dti),DataWidth +1);
							 
                      st0cRegr(DataWidth  downto 3) <= CoeftGetRe(coef);
							 st0cRegi(DataWidth  downto 3) <= CoeftGetIm(coef);
							 
							 st0cRegr(2 downto 0) <= (others => '0');
							 st0cRegi(2 downto 0) <= (others => '0');
               end if;
               
               if falling_edge(clk) then
                    neg0Reg <= neg;
               end if;
           end process st0;
          
           
           --
        --neg read in the second stage
        st1:   process(clk) is
				--	variable r : signed(2*(DataWidth + 1) -1 downto 0);
           begin
               if rising_edge(clk) then
                   --
                   --pd0Reg <= DtMulCoef(DtGetIm(st0dReg), CoeftGetRe(st0cReg)); 
                   if neg0Reg = '1' then
						    pd0reg <= -scaleMul(st0dRegi,st0cRegr);
						    st1dRegr <= - st0dRegr;
						    st1dRegi <= - st0dRegi;
						 else
						    pd0reg <= scaleMul(st0dRegi,st0cRegr);
						    st1dRegr <= st0dRegr;
						    st1dRegi <= st0dRegi;
						 end if;
                   --
                   
                   
                   st1cRegr <= st0cRegr;
                   st1cRegi <= st0cRegi;
                   
                   neg0Reg <= neg1Reg;
                   
               end if;
           end process st1;
           
        st2:   process(clk) is
           begin
               if rising_edge(clk) then
                   --
--                   st2dReg <= CreateDt(
--								DtSubAdd(DtGetRe(st1dReg), pd0Reg), 
--								DtGetIm(st1dReg));
                  --if neg1Reg = '1' then
                     --st2dRegr <= st1dRegr + pd0Reg;
						--else
						   st2dRegr <= st1dRegr - pd0Reg;
						--end if;
						st2dRegi <= st1dRegi;
                   --
                   st2cRegr <= st1cRegr;
                   st2cRegi <= st1cRegi;
                   
               end if;
           end process st2;
        
        st3:   process(clk) is
           begin
               if rising_edge(clk) then
                   --
                   --pd1Reg <= DtMulCoef(DtGetRe(st2dReg), CoeftGetIm(st2cReg));
						 pd1Reg <= scaleMul(st2dRegr, st2cRegi);
                   --
                   st3dRegr <= st2dRegr;
                   st3cRegr <= st2cRegr;
						 
						 st3dRegi <= st2dRegi;
                   st3cRegi <= st2cRegi;
                   
               end if;
           end process st3;
           
        st4:   process(clk) is
           begin
               if rising_edge(clk) then
                   --
--                   st4dReg <= CreateDt(
--								DtGetRe(st3dReg), 
--								DtSubAdd(DtGetIm(st3dReg), pd1Reg));
						st4dRegr <= st3dRegr;
						st4dRegi <= st3dRegi - pd1Reg;
                   --
                   --st4cReg <= CoeftGetRe(st3cReg);
						 st4cReg <= st3cRegr;
                   
               end if;
           end process st4;
        
        st5:   process(clk) is
           begin
               if rising_edge(clk) then
                   --
                   --pd2Reg <= DtMulCoef(DtGetIm(st4dReg), st4cReg); 
						 pd2Reg <= scaleMul(st4dRegi, st4cReg);
                   --
                   st5dRegr <= st4dRegr;
						 st5dRegi <= st4dRegi;
                   
               end if;
           end process st5;
        
        oLatch:   process(clk, st5dRegr, st5dRegi, pd2Reg) is
				variable r : signed(DataWidth downto 0);
           begin
              if clk = '0' then
                  
						r := st5dRegr + pd2Reg;
									dto <= CreateDt(
										r(DataWidth -1 downto 0),
										st5dRegi(DataWidth -1 downto 0)
									);
              end if;
           end process oLatch;
                   --
                   --
                   
        
     
    end architecture ifftbehavior;


architecture passby of fftLS is
     
       
       signal st0dRegr : signed(DataWidth downto 0);
       signal st1dRegr : signed(DataWidth downto 0); 
       signal st2dRegr : signed(DataWidth downto 0); 
       signal st3dRegr : signed(DataWidth downto 0);
       signal st4dRegr : signed(DataWidth downto 0);
       signal st5dRegr : signed(DataWidth downto 0);
		 
		 signal st0dRegi : signed(DataWidth downto 0);
       signal st1dRegi : signed(DataWidth downto 0); 
       signal st2dRegi : signed(DataWidth downto 0); 
       signal st3dRegi : signed(DataWidth downto 0);
       signal st4dRegi : signed(DataWidth downto 0);
       signal st5dRegi : signed(DataWidth downto 0);
       
     
		
       --signal st5cReg : slvCoeft;
    begin
        --  td.re := d.re + d.im * c.re;
		  --  td.im := d.im + td.re * c.im;
		  --  td.re := td.re + td.im * c.re;
		  
        st0:   process(clk) is
           begin
               if rising_edge(clk) then
                      st0dRegr <= conv_signed(DtGetRe(dti),DataWidth +1);
                      st0dRegi <= conv_signed(DtGetIm(dti),DataWidth +1);
				   end if;
            
           end process st0;
        --neg read in the second stage
        st1:   process(clk) is
				--	variable r : signed(2*(DataWidth + 1) -1 downto 0);
           begin
               if rising_edge(clk) then
                   --
                    --
                   st1dRegr <= st0dRegr;
						 st1dRegi <= st0dRegi;
                  end if;
           end process st1;
           
        st2:   process(clk) is
           begin
               if rising_edge(clk) then
        	         st2dRegr <= st1dRegr;
						st2dRegi <= st1dRegi;
                
               end if;
           end process st2;
        
        st3:   process(clk) is
           begin
               if rising_edge(clk) then
                   st3dRegr <= st2dRegr;
						 st3dRegi <= st2dRegi;
               end if;
           end process st3;
           
        st4:   process(clk) is
           begin
               if rising_edge(clk) then
                  
						st4dRegr <= st3dRegr;
						st4dRegi <= st3dRegi;
               end if;
           end process st4;
        
        st5:   process(clk) is
           begin
               if rising_edge(clk) then
                  
                 
                   st5dRegr <= st4dRegr;
						 st5dRegi <= st4dRegi;
               
               end if;
           end process st5;
        
        oLatch:   process(clk, st5dRegr, st5dRegi) is
				variable r : signed(DataWidth downto 0);
           begin
              if clk = '0' then
						dto <= CreateDt(
							st5dRegr(DataWidth -1 downto 0),
							st5dRegi(DataWidth -1 downto 0));
						
              end if;
           end process oLatch;
                   --
                   --
                   
        
     
    end architecture passby;