fftcnt.vhd

来自「基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256」· VHDL 代码 · 共 47 行

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	
library work;
	use work.fftDef.all;	

entity fftCnt is
	port(
			clk, rst : in std_logic;
			enable : in std_logic;
			--
			passfinish : out std_logic;
			cnto : out slvAddrt
		);
end entity fftCnt;

architecture rtl of fftCnt is
	begin
	counter: process(rst, clk) is
				variable cntReg : slvAddrt;
				variable oldpfin : std_logic;
			begin
				if rst = '1' then
					cntReg := (others => '0');
				elsif rising_edge(clk) then
					--
					cnto <= cntReg;
					--
					--cntReg(addrw -1 -1) := '0';
					--
					if enable = '1' then
						cntReg := cntReg +1;
					end if;
					--
				   passfinish <= cntReg(addrw -1 -1) xor oldpfin ;
				   oldpfin := cntReg(addrw -1 -1);
				end if;
				---
				
				---
			end process counter;
	end architecture;