fftdef.vhd

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library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--


--defintion
package fftDef is
	--
	constant Addrw : natural := 8;
	constant pstDw : natural := 16;
	constant fftRdx : natural := 4;
	--
	subtype slvAddrt is unsigned(Addrw -1 downto 0);
	subtype slvBRAddrt is unsigned(Addrw -3 downto 0);
	---
	subtype slvSct is unsigned(Addrw/2-1 downto 0);--(Addrw/2 -1  downto 0);
	---
	---
	--pipeline length of fft processor
	--adg->rdmen&rdcof->fft4st1->fft4st2->rotst1->rotst2->wrback
	--7 stage
	constant plsts : natural := 10; 
	--
	--get real, get imagine
end package fftDef;

package body  fftDef is
end package body fftDef;