fftpll.vhd

来自「基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256」· VHDL 代码 · 共 64 行

library IEEE;	
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;


entity fftPLL is
	port(
			rst, clk : in std_logic;
			agufin : in std_logic;
			start : in std_logic;
			
			--agurst : out std_logic;
			
			
			
			plfin :out std_logic;
			aguen, rden, coren :out std_logic
		);
end entity fftPLL;

architecture std_behavior of fftPLL is
       signal entv : std_logic; --
       signal enReg : std_logic_vector( plsts downto 0);
	begin
	    --
	   --  
	PLCL: process(rst,clk, start,agufin) is
			
		begin
		   --
			--wren <= enReg(1);
			--shifter
			--use to enable the pipleline stage
			if rst ='1' then
				enReg <= (others => '0');
			elsif rising_edge(clk) then
				enReg <= entv & enReg(enReg'left downto 1);  --is ok according to the ise template
			end if;
			
			--
			if rst = '1' then
				entv <= '0';
			elsif start = '1' then
				entv <= '1'; 
			elsif agufin = '1' then
			   entv <= '0';
			end if;

			--
		end process PLCL;
		
		---
		plfin <=  (not enReg(1)) and enReg(0); --enReg(1 downto 0) = "01"
		aguen <= enReg(enReg'left  ) ; --'
		rden <= enReg(enReg'left -1 ) ; --'
		coren <= enReg(enReg'left -2 ) ; -- or enReg(2)); --'
		---
	end architecture std_behavior;