fftsft.vhd

来自「基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256」· VHDL 代码 · 共 58 行

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	
library work;
	use work.fftDef.all;	
	
entity fftSft is
	port ( 
			clk, rst : in std_logic;
			enable : in std_logic;
			shift : in std_logic;
			sfto : out slvSct;
			sftov : out std_logic
		);
end entity fftSft;

architecture rtl of fftSft is
      constant sftc11 : slvSct := (0 => '1', others => '0');
		signal sftReg : slvSct;--std_logic_vector(addrw/2 downto 0);
	begin
	shifter: process(rst,  clk) is	
			begin
				if rst = '1' then
					sftReg <= (sftReg'left => '1', others => '0');--(addrw/2 => '1', others => '0');
					--sfto <= (others => '0');
					sftov <= '0';
				--elsif rising_edge(shift) then
				elsif rising_edge(clk) then
					if shift =  '1' then
						--sftReg <= '1' & sftReg(addrw/2 downto 1); --is ok according to the ise template
					   sftReg <= sftReg(0) & sftReg(addrw/2-1 downto 1); --+ 1;
					end if;
				
				   if (shift = '1') and (sftReg = sftc11) then
					      sftov <=  '1';
					else
					      sftov <= '0';
					end if;
					
				end if;
			end process shifter;
			
			sfto <= sftReg;
			
	---
	--oReg:	process(clk) is
--			begin
--				if rising_edge(clk) then
--					sfto <= sftReg(addrw/2 downto 1);
--				end if;
--			end process oReg;
--		sftov <= sftReg(0);
	end architecture rtl;