fftls.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;	
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;
	
entity fftLS is
	port(
			clk : in std_logic;
			dti : in slvDt;
			coef: in slvCoeft;
			neg : in std_logic;
			xc  : in std_logic;
			dto : out slvDt
		);
end entity fftLS;

architecture behavior of fftLS is
       signal neg0Reg : std_logic;
       signal neg1Reg : std_logic;
       signal neg2Reg : std_logic;
       signal neg3Reg : std_logic;
       signal neg4Reg : std_logic;
       signal neg5Reg : std_logic;
       
       signal xc0Reg : std_logic;
       signal xc1Reg : std_logic;
       signal xc2Reg : std_logic;
       signal xc3Reg : std_logic;
       signal xc4Reg : std_logic;
       signal xc5Reg : std_logic;
       
       signal pd0Reg : signed(DataWidth downto 0);
       signal pd1Reg : signed(DataWidth downto 0);
       signal pd2Reg : signed(DataWidth downto 0);
       
       signal st0dRegr : signed(DataWidth downto 0);
       signal st1dRegr : signed(DataWidth downto 0); 
       signal st2dRegr : signed(DataWidth downto 0); 
       signal st3dRegr : signed(DataWidth downto 0);
       signal st4dRegr : signed(DataWidth downto 0);
       signal st5dRegr : signed(DataWidth downto 0);
		 
		 signal st0dRegi : signed(DataWidth downto 0);
       signal st1dRegi : signed(DataWidth downto 0); 
       signal st2dRegi : signed(DataWidth downto 0); 
       signal st3dRegi : signed(DataWidth downto 0);
       signal st4dRegi : signed(DataWidth downto 0);
       signal st5dRegi : signed(DataWidth downto 0);
       
       signal st0cRegr : signed(DataWidth downto 0);
       signal st1cRegr : signed(DataWidth downto 0);
       signal st2cRegr : signed(DataWidth downto 0);
       signal st3cRegr : signed(DataWidth downto 0);
       
		 signal st0cRegi : signed(DataWidth downto 0);
       signal st1cRegi : signed(DataWidth downto 0);
       signal st2cRegi : signed(DataWidth downto 0);
       signal st3cRegi : signed(DataWidth downto 0);
       
		 
		 signal st4cReg : signed(DataWidth downto 0); 
		 
		 function scaleMul(d, c :signed) return signed is
				variable r : signed(d'length + c'length -1 downto 0); 
--				variable dd,dc,dr,mul, eps : real;
--				variable cr : signed(DataWidth -1 downto 0);
			begin
				r := d * c;
				r := r(r'left -1 downto 0) & '0';
				return r(r'left downto r'left - d'length +1);
			end function scaleMul;
       --signal st5cReg : slvCoeft;
    begin
        --  td.re := d.re + d.im * c.re;
		  --  td.im := d.im + td.re * c.im;
		  --  td.re := td.re + td.im * c.re;
		  
        st0:   process(clk) is
           begin
               if rising_edge(clk) then
                      st0dRegr <= conv_signed(DtGetRe(dti),DataWidth +1);
                      st0dRegi <= conv_signed(DtGetIm(dti),DataWidth +1);
							 
                      st0cRegr(DataWidth  downto 3) <= CoeftGetRe(coef);
							 st0cRegi(DataWidth  downto 3) <= CoeftGetIm(coef);
							 
							 st0cRegr(2 downto 0) <= (others => '0');
							 st0cRegi(2 downto 0) <= (others => '0');
              
                      neg0Reg <= neg;
                      xc0Reg <= xc;
               end if;
           end process st0;
        --neg read in the second stage
        st1:   process(clk) is
				--	variable r : signed(2*(DataWidth + 1) -1 downto 0);
           begin
               if rising_edge(clk) then
                   --
                   --pd0Reg <= DtMulCoef(DtGetIm(st0dReg), CoeftGetRe(st0cReg)); 
						 if xc0Reg = '0' then
						    pd0reg <= scaleMul(st0dRegi,st0cRegr);
						 else
						    pd0reg <= (others => '0');   
                   end if;
                   
                   st1dRegr <= st0dRegr;
                   st1cRegr <= st0cRegr;
						 
						 st1dRegi <= st0dRegi;
                   st1cRegi <= st0cRegi;
                   --
                   neg1Reg <= neg0Reg;
                   xc1Reg <= xc0Reg;
               end if;
           end process st1;
           
        st2:   process(clk) is
           begin
               if rising_edge(clk) then
                   --
--                   st2dReg <= CreateDt(
--								DtSubAdd(DtGetRe(st1dReg), pd0Reg), 
--								DtGetIm(st1dReg));
                  
						 st2dRegr <= st1dRegr + pd0Reg;
						
						 st2dRegi <= st1dRegi;
                   --
                   st2cRegr <= st1cRegr;
                   st2cRegi <= st1cRegi;
                   --
                   neg2Reg <= neg1Reg;
                   xc2Reg <= xc1Reg;
               end if;
           end process st2;
        
        st3:   process(clk) is
           begin
               if rising_edge(clk) then
                   --
                   --pd1Reg <= DtMulCoef(DtGetRe(st2dReg), CoeftGetIm(st2cReg));
						 if xc2Reg = '0' then
						    pd1Reg <= scaleMul(st2dRegr, st2cRegi);
						 else
						    pd1reg <= (others => '0');
                   end if;
                   --
                   st3dRegr <= st2dRegr;
                   st3cRegr <= st2cRegr;
						 
						 st3dRegi <= st2dRegi;
                   st3cRegi <= st2cRegi;
                   --
                   neg3Reg <= neg2Reg;
                   xc3Reg <= xc2Reg;
               end if;
           end process st3;
           
        st4:   process(clk) is
           begin
               if rising_edge(clk) then
                   --
--                   st4dReg <= CreateDt(
--								DtGetRe(st3dReg), 
--								DtSubAdd(DtGetIm(st3dReg), pd1Reg));
						st4dRegr <= st3dRegr;
					
						st4dRegi <= st3dRegi + pd1Reg;
						
                   --
                   --st4cReg <= CoeftGetRe(st3cReg);
						 st4cReg <= st3cRegr;
                   --
                   neg4Reg <= neg3Reg;
                   xc4Reg <= xc3Reg;
               end if;
           end process st4;
        
        st5:   process(clk) is
           begin
               if rising_edge(clk) then
                   --
                   --pd2Reg <= DtMulCoef(DtGetIm(st4dReg), st4cReg);
                   if xc4Reg = '0' then 
						    pd2Reg <= scaleMul(st4dRegi, st4cReg);
						 else
						    pd2reg <= (others => '0');
						 end if;
                   --
                   st5dRegr <= st4dRegr;
						 st5dRegi <= st4dRegi;
                   --
                   neg5Reg <= neg4Reg;
                   xc5Reg <= xc4Reg;
               end if;
           end process st5;
        
        oLatch:   process(st5dRegr, st5dRegi, pd2Reg, neg5Reg) is
				variable r : signed(DataWidth downto 0);
           begin
              --if clk = '0' then
                if xc5Reg = '0' then
						r := st5dRegr + pd2Reg;
                  case neg5Reg is
                      when '1' =>
									dto <= CreateDt(
										DtSubNeg(r(DataWidth -1 downto 0)),
										DtSubNeg(st5dRegi(DataWidth -1 downto 0))
									);
                      when '0' =>
									dto <= CreateDt(
										r(DataWidth -1 downto 0),
										st5dRegi(DataWidth -1 downto 0)
									);
							when others =>
								dto <= (others => '-');
                  end case; 
                else
                   dto <= CreateDt(
										st5dRegi(DataWidth -1 downto 0),
										DtSubNeg(st5dRegr(DataWidth -1 downto 0))
									);
                end if;
              --end if;
           end process oLatch;
                   --
                   --
                   
        
     
    end architecture behavior;

architecture ifftbehavior of fftLS is
       signal neg0Reg : std_logic;
       signal neg1Reg : std_logic;
       
       signal pd0Reg : signed(DataWidth downto 0);
       signal pd1Reg : signed(DataWidth downto 0);
       signal pd2Reg : signed(DataWidth downto 0);
       
       signal st0dRegr : signed(DataWidth downto 0);
       signal st0dRegi : signed(DataWidth downto 0);
       
       signal st0dRegrt : slvDtSub;--signed(DataWidth downto 0);
       signal st0dRegit : slvDtSub;--signed(DataWidth downto 0);
       
       
       signal st1dRegr : signed(DataWidth downto 0); 
       signal st2dRegr : signed(DataWidth downto 0); 
       signal st3dRegr : signed(DataWidth downto 0);
       signal st4dRegr : signed(DataWidth downto 0);
       signal st5dRegr : signed(DataWidth downto 0);
		 
		 
       signal st1dRegi : signed(DataWidth downto 0); 
       signal st2dRegi : signed(DataWidth downto 0);