fftbut.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;

-- 2 level pipelined radix-4 butterfly
entity fftBut is
	port( 
			clk : in std_logic;
			rddt0,rddt1,rddt2,rddt3 : in slvDt;
			bufo0,bufo1,bufo2,bufo3 : out slvDt
		);	
end entity fftBut;

architecture std_behavior of fftBut is
		signal bfst1do0r, bfst1do1r, bfst1do2r, bfst1do3r : signed(DataWidth +1 downto 0);
		signal bfst1do0i, bfst1do1i, bfst1do2i, bfst1do3i : signed(DataWidth +1 downto 0);
		
		signal st1DtReg0r, st1DtReg1r, st1DtReg2r, st1DtReg3r : signed(DataWidth +1 downto 0);
		signal st1DtReg0i, st1DtReg1i, st1DtReg2i, st1DtReg3i : signed(DataWidth +1 downto 0);
		
		signal st2DtReg0r, st2DtReg1r, st2DtReg2r, st2DtReg3r : signed(DataWidth +1 downto 0);
		signal st2DtReg0i, st2DtReg1i, st2DtReg2i, st2DtReg3i : signed(DataWidth +1 downto 0);

--		signal adder0ia, adder0ib, adder0o,
--		        adder1ia, adder1ib, adder1o,
--		        suber0ia, suber0ib, suber0o,
--		        suber1ia, suber1ib, suber1o : slvDt; 
	begin 
		FFT4Reg: process(clk) is		
			begin	
				if rising_edge(clk) then
				--conv_signed(DtGetRe(a),DataWidth +1)
					st1DtReg0r <= conv_signed(DtGetRe(rddt0),DataWidth +2);
					st1DtReg0i <= conv_signed(DtGetIm(rddt0),DataWidth +2);
				--	
					st1DtReg1r <= conv_signed(DtGetRe(rddt1),DataWidth +2);
					st1DtReg1i <= conv_signed(DtGetIm(rddt1),DataWidth +2);
				--
					st1DtReg2r <= conv_signed(DtGetRe(rddt2),DataWidth +2);
					st1DtReg2i <= conv_signed(DtGetIm(rddt2),DataWidth +2);
				--	
					st1DtReg3r <= conv_signed(DtGetRe(rddt3),DataWidth +2);
					st1DtReg3i <= conv_signed(DtGetIm(rddt3),DataWidth +2);
				end if;
				
				if falling_edge(clk) then
		            st2DtReg0r <= bfst1do0r;
		            st2DtReg0i <= bfst1do0i;
						--
						st2DtReg1r <= bfst1do1r;
						st2DtReg1i <= bfst1do1i;
						--
						st2DtReg2r <= bfst1do2r;
						st2DtReg2i <= bfst1do2i;
						--st2DtReg3r <= DtRotJ(bfst1do3);
						st2DtReg3r <= -bfst1do3i;
						st2DtReg3i <= bfst1do3r;
				end if;
			end process FFT4Reg;
--		--DtRotJ(
--		Adder0: entity work.fftScaleAddSub (behavior) generic map(IsAdder => true)
--          port map( A => adder0ia, B => adder0ib,  C => adder0o); 
--		Adder1: entity work.fftScaleAddSub (behavior) generic map(IsAdder => true)
--          port map( A => adder1ia, B => adder1ib,  C => adder1o);
--      Suber0: entity work.fftScaleAddSub (behavior) generic map(IsAdder => false)
--          port map( A => suber0ia, B => suber0ib,  C => suber0o);  
--      Suber1: entity work.fftScaleAddSub (behavior) generic map(IsAdder => false)
--          port map( A => suber1ia, B => suber1ib,  C => suber1o);    
		---latch for st1 out put
		FFT4MUX: process(clk,st1DtReg0r, st1DtReg1r, st1DtReg2r, st1DtReg3r
		                     ,st2DtReg0r, st2DtReg1r, st2DtReg2r, st2DtReg3r,
									st1DtReg0i, st1DtReg1i, st1DtReg2i, st1DtReg3i
		                     ,st2DtReg0i, st2DtReg1i, st2DtReg2i, st2DtReg3i
		                   ) is
				variable r, i: signed(DataWidth +1 downto 0);
			begin
				case clk is
				    when '1' =>
					--bfst1do0 <= DtAdd(st1DtReg0, st1DtReg2)/2.0;
					bfst1do0r <= st1DtReg0r + st1DtReg2r;
					bfst1do0i <= st1DtReg0i + st1DtReg2i;
					
					--bfst1do2 <= DtSub(st1DtReg0, st1DtReg2)/2.0;
					bfst1do2r <= st1DtReg0r - st1DtReg2r;
					bfst1do2i <= st1DtReg0i - st1DtReg2i;
					
					--bfst1do1 <= DtAdd(st1DtReg1, st1DtReg3)/2.0;
					bfst1do1r <= st1DtReg1r + st1DtReg3r;
					bfst1do1i <= st1DtReg1i + st1DtReg3i;
					
					--bfst1do3 <= DtSub(st1DtReg1, st1DtReg3)/2.0;
					bfst1do3r <= st1DtReg1r - st1DtReg3r;
					bfst1do3i <= st1DtReg1i - st1DtReg3i;
					
				    when others =>
					--butterfly
					--bufo0 <= DtAdd(st2DtReg0, st2DtReg1)/2.0;
					r := (st2DtReg0r + st2DtReg1r);
					i := (st2DtReg0i + st2DtReg1i);
					bufo0 <= 
							conv_std_logic_vector(r(DataWidth + 1 downto 2),DataWidth)
							&
							conv_std_logic_vector(i(DataWidth + 1 downto 2),DataWidth);
					--bufo1 <= DtSub(st2DtReg2, DtRotJ(st2DtReg3))/2.0;  --rot j
					r :=(st2DtReg2r - st2DtReg3r);
					i :=(st2DtReg2i - st2DtReg3i);
					bufo1 <= 
							conv_std_logic_vector(r(DataWidth + 1 downto 2),DataWidth)
							&
							conv_std_logic_vector(i(DataWidth + 1 downto 2),DataWidth);
					--bufo2 <= DtSub(st2DtReg0, st2DtReg1)/2.0;
					r :=(st2DtReg0r - st2DtReg1r);
					i :=(st2DtReg0i - st2DtReg1i);
					bufo2 <= 
							conv_std_logic_vector(r(DataWidth + 1 downto 2),DataWidth)
							&
							conv_std_logic_vector(i(DataWidth + 1 downto 2),DataWidth);
					--bufo3 <= DtAdd(st2DtReg2, DtRotJ(st2DtReg3))/2.0;  --rot j
					r :=(st2DtReg2r + st2DtReg3r);
					i :=(st2DtReg2i + st2DtReg3i);
					bufo3 <= 
							conv_std_logic_vector(r(DataWidth + 1 downto 2),DataWidth)
							&
							conv_std_logic_vector(i(DataWidth + 1 downto 2),DataWidth);
				end case;
			end process FFT4MUX;
			
	end architecture std_behavior;
	
architecture ifft_behavior of fftBut is
		signal bfst1do0r, bfst1do1r, bfst1do2r, bfst1do3r : signed(DataWidth +1 downto 0);
		signal bfst1do0i, bfst1do1i, bfst1do2i, bfst1do3i : signed(DataWidth +1 downto 0);
		
		signal st1DtReg0r, st1DtReg1r, st1DtReg2r, st1DtReg3r : signed(DataWidth +1 downto 0);
		signal st1DtReg0i, st1DtReg1i, st1DtReg2i, st1DtReg3i : signed(DataWidth +1 downto 0);
		
		signal st2DtReg0r, st2DtReg1r, st2DtReg2r, st2DtReg3r : signed(DataWidth +1 downto 0);
		signal st2DtReg0i, st2DtReg1i, st2DtReg2i, st2DtReg3i : signed(DataWidth +1 downto 0);

--		signal adder0ia, adder0ib, adder0o,
--		        adder1ia, adder1ib, adder1o,
--		        suber0ia, suber0ib, suber0o,
--		        suber1ia, suber1ib, suber1o : slvDt; 
	begin 
		FFT4Reg: process(clk) is		
			begin	
				if rising_edge(clk) then
				--conv_signed(DtGetRe(a),DataWidth +1)
					st1DtReg0r <= conv_signed(DtGetRe(rddt0),DataWidth +2);
					st1DtReg0i <= conv_signed(DtGetIm(rddt0),DataWidth +2);
				--	
					st1DtReg1r <= conv_signed(DtGetRe(rddt1),DataWidth +2);
					st1DtReg1i <= conv_signed(DtGetIm(rddt1),DataWidth +2);
				--
					st1DtReg2r <= conv_signed(DtGetRe(rddt2),DataWidth +2);
					st1DtReg2i <= conv_signed(DtGetIm(rddt2),DataWidth +2);
				--	
					st1DtReg3r <= conv_signed(DtGetRe(rddt3),DataWidth +2);
					st1DtReg3i <= conv_signed(DtGetIm(rddt3),DataWidth +2);
				end if;
				
				if falling_edge(clk) then
		            st2DtReg0r <= bfst1do0r;
		            st2DtReg0i <= bfst1do0i;
						--
						st2DtReg1r <= bfst1do1r;
						st2DtReg1i <= bfst1do1i;
						--
						st2DtReg2r <= bfst1do2r;
						st2DtReg2i <= bfst1do2i;
						--st2DtReg3r <= DtRotJ(bfst1do3);
						st2DtReg3r <= -bfst1do3i;
						st2DtReg3i <= bfst1do3r;
				end if;
			end process FFT4Reg;
--		--DtRotJ(
--		Adder0: entity work.fftScaleAddSub (behavior) generic map(IsAdder => true)
--          port map( A => adder0ia, B => adder0ib,  C => adder0o); 
--		Adder1: entity work.fftScaleAddSub (behavior) generic map(IsAdder => true)
--          port map( A => adder1ia, B => adder1ib,  C => adder1o);
--      Suber0: entity work.fftScaleAddSub (behavior) generic map(IsAdder => false)
--          port map( A => suber0ia, B => suber0ib,  C => suber0o);  
--      Suber1: entity work.fftScaleAddSub (behavior) generic map(IsAdder => false)
--          port map( A => suber1ia, B => suber1ib,  C => suber1o);    
		---latch for st1 out put
		FFT4MUX: process(clk,st1DtReg0r, st1DtReg1r, st1DtReg2r, st1DtReg3r
		                     ,st2DtReg0r, st2DtReg1r, st2DtReg2r, st2DtReg3r,
									st1DtReg0i, st1DtReg1i, st1DtReg2i, st1DtReg3i
		                     ,st2DtReg0i, st2DtReg1i, st2DtReg2i, st2DtReg3i
		                   ) is
				variable r, i: signed(DataWidth +1 downto 0);
			begin
				case clk is
				    when '1' =>
					--bfst1do0 <= DtAdd(st1DtReg0, st1DtReg2)/2.0;
					bfst1do0r <= st1DtReg0r + st1DtReg2r;
					bfst1do0i <= st1DtReg0i + st1DtReg2i;
					
					--bfst1do2 <= DtSub(st1DtReg0, st1DtReg2)/2.0;
					bfst1do2r <= st1DtReg0r - st1DtReg2r;
					bfst1do2i <= st1DtReg0i - st1DtReg2i;
					
					--bfst1do1 <= DtAdd(st1DtReg1, st1DtReg3)/2.0;
					bfst1do1r <= st1DtReg1r + st1DtReg3r;
					bfst1do1i <= st1DtReg1i + st1DtReg3i;
					
					--bfst1do3 <= DtSub(st1DtReg1, st1DtReg3)/2.0;
					bfst1do3r <= st1DtReg1r - st1DtReg3r;
					bfst1do3i <= st1DtReg1i - st1DtReg3i;
					
				    when others =>
					--butterfly
					--bufo0 <= DtAdd(st2DtReg0, st2DtReg1)/2.0;
					r := (st2DtReg0r + st2DtReg1r);
					i := (st2DtReg0i + st2DtReg1i);
					bufo0 <= 
							conv_std_logic_vector(r(DataWidth - 1 downto 0),DataWidth)
							&
							conv_std_logic_vector(i(DataWidth - 1 downto 0),DataWidth);
					--bufo1 <= DtSub(st2DtReg2, DtRotJ(st2DtReg3))/2.0;  --rot j
					r :=(st2DtReg2r - st2DtReg3r);
					i :=(st2DtReg2i - st2DtReg3i);
					bufo1 <= 
							conv_std_logic_vector(r(DataWidth - 1 downto 0),DataWidth)
							&
							conv_std_logic_vector(i(DataWidth - 1 downto 0),DataWidth);
					--bufo2 <= DtSub(st2DtReg0, st2DtReg1)/2.0;
					r :=(st2DtReg0r - st2DtReg1r);
					i :=(st2DtReg0i - st2DtReg1i);
					bufo2 <= 
							conv_std_logic_vector(r(DataWidth - 1 downto 0),DataWidth)
							&
							conv_std_logic_vector(i(DataWidth - 1 downto 0),DataWidth);
					--bufo3 <= DtAdd(st2DtReg2, DtRotJ(st2DtReg3))/2.0;  --rot j
					r :=(st2DtReg2r + st2DtReg3r);
					i :=(st2DtReg2i + st2DtReg3i);
					bufo3 <= 
							conv_std_logic_vector(r(DataWidth - 1 downto 0),DataWidth)
							&
							conv_std_logic_vector(i(DataWidth - 1 downto 0),DataWidth);
				end case;
			end process FFT4MUX;
			
	end architecture ifft_behavior;