fftfifo.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	
library work;
	use work.fftDef.all;	

entity fftFiFo is
	generic ( plDel : natural := plsts -1);
	port( 
			clk : in std_logic;
			addri0, addri1, addri2, addri3 : in slvAddrt;
			enable : in std_logic;
			rda0, rda1, rda2, rda3 : out slvAddrt;
			wra0, wra1, wra2, wra3 : out slvAddrt;
			wren : out std_logic
		);
end entity fftFiFo;

architecture behavior of fftFiFo is
		type adlst is array(plDel -1 downto 0) of slvAddrt;
		signal adlst0, adlst1, adlst2, adlst3 : adlst;
		signal enableReg : std_logic_vector(plDel -2 downto 0);
	begin
		------------
		enReg:	process(clk) is
			begin
				if rising_edge(clk) then
					enableReg <= enable & enableReg(enableReg'left downto 1); --is ok according to the ise template
				end if;
			end process enReg;
		------------
		--memory write enable register
		wren <= enableReg(0);
		------------
		rda0 <= adlst0(0);
		rda1 <= adlst1(0);
		rda2 <= adlst2(0);
		rda3 <= adlst3(0);
		------------
		wra0 <= adlst0(adlst'left);
		wra1 <= adlst1(adlst'left);
		wra2 <= adlst2(adlst'left);
		wra3 <= adlst3(adlst'left);
		------------
		addrArray: for i in adlst'range generate --'
				fist :if i = 0 generate
				dff: process(clk) is
					begin
						if rising_edge(clk) then
							adlst0(i) <= addri0;
							adlst1(i) <= addri1;
							adlst2(i) <= addri2;
							adlst3(i) <= addri3;
						end if;
					end process dff;
				end generate;
				---
				other :if i /= 0 generate
				dff: process(clk) is
					begin
						if rising_edge(clk) then
							adlst0(i) <= adlst0(i-1);
							adlst1(i) <= adlst1(i-1);
							adlst2(i) <= adlst2(i-1);
							adlst3(i) <= adlst3(i-1);
						end if;
					end process dff;
				end generate;
			end generate;
		-----------
	end architecture;