fftcore.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;
	
entity fftCore is
   generic (ifft : boolean := false);
	port(
	      rst : in std_logic;
			clk : in std_logic;
			coefk1 : in slvAddrt;
			enable : in std_logic;
			lastpass : in std_logic;
			dti0, dti1, dti2, dti3 : in slvDt;
			--
			dto0, dto1, dto2, dto3 : out slvDt;
			--
			inrdy : out std_logic;
			
			--
			outvld : out std_logic
		);	
end entity fftCore;

architecture std_structure of fftCore is  
		--signal of fft4st2
		signal bfst2do0, bfst2do1, bfst2do2, bfst2do3 : slvDt;
		--
		signal coefo1,coefo2,coefo3 : slvCoeft;
		--
		signal romen : std_logic;
		--
      signal lstpReg : std_logic_vector(7 downto 0); --7
      signal enReg : std_logic_vector(5 downto 0);
      signal xc2, xc3 : std_logic;
      signal neg2, neg3 : std_logic;
      --
	begin
	   LSTPCTRL:   process(rst, clk) is
	      begin
	         if rst = '1' then
	             lstpReg <= (others => '0');
	             enReg <= (others => '0');
	         elsif rising_edge(clk) then
	            lstpReg <= lastpass & lstpReg(lstpReg'left downto 1);
	            enReg <= enable & enReg(enReg'left downto 1);
	         end if;
	      end process LSTPCTRL;
	   ----input ready
	   inrdy <= lstpReg(1);--lstpReg(0);-- and lstpReg(1);
	   ----out put valid
	   outvld <= lstpReg(1);--lstpReg(0) and lstpReg(1);
	   ---it's no need to look up coeficient at the last pass
		--change for debug
	   romen <= enable;-- and not lstpReg(lstpReg'left); 
	   
		CoefRom: 	entity work.fftCRom (std_behavior)
					port map(clk => clk, enable => romen,
							coefk1 => coefk1,
							coefo1 => coefo1, coefo2 => coefo2, coefo3 => coefo3,
							neg2 => neg2, neg3 => neg3,
							xc2 => xc2, xc3 => xc3);
		
		fftbutterfly: if ifft = false generate
		butterfly:	entity work.fftBut (std_behavior)
		         --generic map (ifft => ifft)
					port map(clk => clk,
							 rddt0 => dti0, rddt1 => dti1, rddt2 =>dti2, rddt3 => dti3,
							 bufo0 => bfst2do0, 
							 bufo1 => bfst2do1,
							 bufo2 => bfst2do2, 
							 bufo3 => bfst2do3
							 );
		end generate;
		
		
		ifftbutterfly: if ifft = true generate
		butterfly:	entity work.fftBut (ifft_behavior)
		         --generic map (ifft => ifft)
					port map(clk => clk,
							 rddt0 => dti0, rddt1 => dti1, rddt2 =>dti2, rddt3 => dti3,
							 bufo0 => bfst2do0, 
							 bufo1 => bfst2do1,
							 bufo2 => bfst2do2, 
							 bufo3 => bfst2do3
							 );
		end generate;
		--					 
		rotator:	entity work.fftRor (std_behavior)
		         generic map (ifft => ifft)
					port map(clk => clk,
							dti0 => bfst2do0, --math_cbase_1, --
							dti1 => bfst2do1, 
							dti2 => bfst2do2, 
							dti3 => bfst2do3,
							xc2 => xc2, xc3 => xc3,
							neg2 => neg2, neg3 => neg3,
							coef1 => coefo1, coef2 => coefo2, coef3 => coefo3,
							dto0 => dto0, dto1 => dto1, dto2 => dto2, dto3 => dto3);
	end architecture std_structure;