fftagu.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	
library work;
	use work.fftDef.all;	

	--the address generation unit
entity fftAgu is
	port(
			clk, rst : in std_logic;
			enable : in std_logic;
			--
			finish :out std_logic;
			lastpass : out std_logic;
			ado0,ado1,ado2,ado3 : out slvAddrt;
			coefko : out slvAddrt
			
			
		);
end entity fftAgu;

architecture std_behavior of fftAgu is
		--
		
		-- signal for counter
		signal cnto : slvAddrt;
		signal passfinish : std_logic;
		-- signal for shifter
		constant sftc10 : slvSct := "0001";
		signal sfto : slvSct;
		signal sftrst : std_logic;
		signal sftov : std_logic;
		
		signal fftidx0, fftidx1, fftidx2, fftidx3 : slvAddrt;
		signal coefk : slvAddrt;	
	begin	
		---
		sftrst <= rst;
		----
		finReg:   process(clk) is
		   begin
		      -- use falling edge to avoid the delay of the finish signal 
		      -- at the rising edge of the clock  
		      if falling_edge(clk) then
		         finish <= sftov;
		      end if;
		   end process finReg;
		---
		OLatch:	process(clk, cnto, sfto,coefk, fftidx0, fftidx1, fftidx2, fftidx3) is
			begin
				if clk = '0' then
					coefko <= coefk;
					ado0 <= fftidx0;
					ado1 <= fftidx1;
					ado2 <= fftidx2;
					ado3 <= fftidx3;
				end if;		
			end process OLatch;
		
		---
		Coef:	entity work.fftCoeflgc (behavioral)
				port map(cnti => cnto, sctrl => sfto, coefko => coefk);
		---
		Addr0:   entity work.fftAddrLgc (behavior)
		         port map(cnti => cnto, sctrl => sfto, idx => "00" , addro => fftidx0 );
		
		Addr1:   entity work.fftAddrLgc (behavior)
		         port map(cnti => cnto, sctrl => sfto, idx => "01" , addro => fftidx1 ); 
		
		Addr2:   entity work.fftAddrLgc (behavior)
		         port map(cnti => cnto, sctrl => sfto, idx => "10" , addro => fftidx2 );  
		
		Addr3:   entity work.fftAddrLgc (behavior)
		         port map(cnti => cnto, sctrl => sfto, idx => "11" , addro => fftidx3 );                       
		---
		
		lastpassReg: process (rst, clk) is
		   begin
		       if rst = '1' then
		          lastpass <= '0';
		       elsif rising_edge(clk) then
		          if sfto = sftc10 then
		              lastpass <= '1';
		          else 
		              lastpass <= '0';
		          end if;
		       end if;
		   end process lastpassReg;
		   
		---
		Cntr:	entity work.fftCnt (rtl)
				port map( clk => clk, rst => rst,
						enable => enable,
						passfinish => passfinish, cnto => cnto);
		---
		sftr:	entity work.fftSft (rtl)
				port map ( clk => clk , rst => rst, enable => enable, shift => passfinish, 
							sfto => sfto, sftov => sftov);
							
		
	end architecture std_behavior;