fftbram.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	
library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;

entity fftBRam is
    generic (Depth : natural);
    port(
           clk : in std_logic;
           --
           rda : in slvBRAddrt;
           rddt : out slvDt;
           --
           wren : in std_logic;
           wra :  in slvBRAddrt;
           wrdt : in slvDt
          );
end entity fftBRam;

architecture behavior of fftBRam is
       type memtype is array (Depth -1 downto 0) of slvDt;
       signal mem : memtype ;
       
       --signal wrReg : slvDt;
    begin
        
        --wraddr:		process(clk) is
		--	begin
		--		if rising_edge(clk) then
		--			wrReg <= wrdt;
		--	end if;
		--end process wraddr;
			
		 --rdLatch:	process(clk) is
			--begin
				--if clk = '0' then 
				--rddt <= mem(conv_integer(rda));	 
				--end if;
			--end process rdLatch;
			
		 dualPortRam	:process (clk) is
			begin
			   if falling_edge(clk) then
               if wren = '1' then 
				      --according to ise, read data assignment should put below, in the "if wren ='1'"
				      --but i think it is not correct.
				      --so i put it out of the "if wren ='1'" statement
				      --rddt <= mem(conv_integer(rda));
					   mem(conv_integer(wra)) <= wrdt;
					end if;
					rddt <= mem(conv_integer(rda));
				end if;
			end process dualPortRam;	
			
	end architecture behavior;