ffttestbench.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	use ieee.std_logic_textio.all;
	
library std;
    use std.textio.all;
	
library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;

entity fftTestBench is
    generic(
             period : time := 10 ns;
             saveresult : boolean := true
             );
end entity fftTestBench;

architecture behavior of fftTestBench is
       signal clk : std_logic:= '1';
       signal rst : std_logic:= '1';
       signal start : std_logic := '0';
       ---
       signal dtvld : std_logic;
       signal dto0, dto1, dto2, dto3 : slvDt;
       ---
       signal inrdy : std_logic;
       signal dti0, dti1, dti2, dti3 : slvDt;
       
       --
       signal dti0t, dti1t, dti2t, dti3t : slvDt;
       
       signal agucnto : slvAddrt;
       signal bufin : slvDt;
       
       signal sdto : slvDt;
       signal sdtovld : std_logic;
    begin
        --
      readinbuf: process(clk, start) is
			file vecinfile : text open read_mode is "fftInput.vec";
			variable vecline: line;
			 variable dtre, dtim : std_logic_vector(DataWidth -1 downto 0);
       begin
          if start = '1' then
              if clk = '1' then
						if not endfile(vecinFile) then
						readline( vecinFile, vecLine);
						read(vecLine, dtre);
						read(vecLine, dtim);
						
						bufin <= CreateDt( slvDtSub(dtre),slvDtSub(dtim));
						
                  end if;
              end if;
           else
              
           end if;
       end process readinbuf;
        --
        
    waveform:   process is
       begin
          wait for period/2;
          clk <= not clk;
          -- reset
          if now < 20 ns then
             rst <= '1';
          else
             rst <= '0';
          end if;
          -- start
          if now < 40 ns or now > 3000 ns then
             start <= '0';
          else
             start <= '1';
          end if;
       end process waveform;
    
    processor:   entity work.fftp (structure)
        generic map(ifft => false) 
        port map(rst =>rst, clk => clk, extclk => clk, start => start,
                 inDt => bufin, dto => sdto,
			        dtvld => sdtovld );

    bufsaveout:   process(clk) is
          file savefile : text open write_mode is "sdataout.vec";
          file binsavefile : text open write_mode is "bindataout2.vec";
          variable txtline : line;
       begin
           
            if falling_edge(clk) then
                if saveresult and sdtovld = '1' then
                   write(txtline, signedToReal(DtGetRe(sdto),DataWidth));
                   write(txtline, '+');
                   write(txtline, signedToReal(DtGetIm(sdto),DataWidth));
                   write(txtline, 'j');
                   
                   writeline(savefile, txtline);
                --else
                   --report "fuck";
                   write(txtline, std_logic_vector(DtGetRe(sdto)));
                   write(txtline, ' ');
                   write(txtline, std_logic_vector(DtGetIm(sdto)));

                   writeline(binsavefile, txtline);
                
               end if;
           end if;
       end process bufsaveout;
       
    end architecture behavior;