fftror.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library IEEE;	
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;
	
entity fftRor is
   generic (ifft : boolean := false);
	port(
			clk : in std_logic;
			dti0,dti1,dti2,dti3 : in slvDt;
			coef1, coef2, coef3 : in slvCoeft;
			xc2, xc3 : in std_logic;
			neg2, neg3 : in std_logic;
			dto0, dto1, dto2, dto3 : out slvDt
		);
end entity fftRor;

architecture std_behavior of fftRor is
		signal inReg0, inReg1, inReg2, inReg3 :slvDt;
		signal tdt0, tdt1, tdt2, tdt3 :slvDt;
		signal neg2s, neg23 : std_logic; 
		
	begin
	ls0:   entity work.fftLS (passby)
	        port map( clk => clk, dti => dti0,
			         coef => (others => '0'),--
			         neg =>'0',
			         xc => '0',
			         dto => dto0
		);
	
	---
	lsFFT:
	if ifft=false generate
	ls1:   entity work.fftLS (behavior)
	        port map( clk => clk, dti => dti1,
			         coef => coef1,
			         neg =>'0',
			         xc => '0',
			         dto => dto1
		);
	
	ls2:   entity work.fftLS (behavior)
	        port map( clk => clk, dti => dti2,
			         coef => coef2,
			         neg => neg2,
			         xc => xc2,
			         dto => dto2
		);
	ls3:   entity work.fftLS (behavior)
	        port map( clk => clk, dti => dti3,
			         coef => coef3,
			         neg => neg3,
			         xc => xc3,
			         dto => dto3
		);
	end generate;
	
--	lsIFFT:
--	if ifft=true generate
--	ls1:   entity work.fftLS (ifftbehavior)
--	        port map( clk => clk, dti => dti1,
--			         coef => coef1,
--			         neg =>'0',
--			         dto => dto1
--		);
--	
--	ls2:   entity work.fftLS (ifftbehavior)
--	        port map( clk => clk, dti => dti2,
--			         coef => coef2,
--			         neg => neg2,
--			         dto => dto2
--		);
--	ls3:   entity work.fftLS (ifftbehavior)
--	        port map( clk => clk, dti => dti3,
--			         coef => coef3,
--			         neg => neg23,
--			         dto => dto3
--		);	
--	end generate;
	
	---
	neg2s <= '1' when (CoeftGetIm(coef2) >0) else '0';
	--neg2 <=  not (CoeftGetIm(coef2)(slvCoeftSub'left));
	--
	---
	neg23 <= '1' when (CoeftGetIm(coef2) >0 or CoeftGetIm(coef3) >0) else '0';
	--neg23 <= (CoeftGetIm(coef2)(slvCoeftSub'left)) nand (CoeftGetIm(coef3)(slvCoeftSub'left));
	--
	
	
	end architecture std_behavior;