fftmem.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;


entity fftMem is
	port(
			clk : in std_logic;
			rda0, rda1, rda2, rda3 : in slvAddrt;
			dto0, dto1, dto2, dto3 : out slvDt;
			wra0, wra1, wra2, wra3 : in slvAddrt;
			wren : in std_logic;
			dti0, dti1, dti2, dti3 : in slvDt
		);
end entity fftMem;

architecture behavior of fftMem is
      constant c00 : std_logic_vector(1 downto 0) := "00";
      constant c01 : std_logic_vector(1 downto 0) := "01";
      constant c10 : std_logic_vector(1 downto 0) := "10";
      constant c11 : std_logic_vector(1 downto 0) := "11";
		
		signal r0ra, r1ra, r2ra, r3ra : slvBRAddrt; --ram 0/1/2/3 read addr
		signal r0rd, r1rd, r2rd, r3rd : slvDt; --ram 0/1/2/3 read data
		
		signal r0wa, r1wa, r2wa, r3wa : slvBRAddrt; --ram 0/1/2/3 read addr
		signal r0wd, r1wd, r2wd, r3wd : slvDt; --ram 0/1/2/3 read data
		signal dti0Reg, dti1Reg, dti2Reg, dti3Reg : slvDt;
		
	begin
		--
		inputReg:	process(clk) is
			begin
				if rising_edge(clk) then
					dti0Reg <= dti0;
					dti1Reg <= dti1;
					dti2Reg <= dti2;
					dti3Reg <= dti3;
				end if;
			end process inputReg;
		--
		ram0:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => clk, rda => r0ra, rddt => r0rd,
                    wren => wren, wra => r0wa, wrdt => r0wd);
      ram1:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => clk, rda => r1ra, rddt => r1rd,
                    wren => wren, wra => r1wa, wrdt => r1wd);
      ram2:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => clk, rda => r2ra, rddt => r2rd,
                    wren => wren, wra => r2wa, wrdt => r2wd);
      ram3:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => clk, rda => r3ra, rddt => r3rd,
                    wren => wren, wra => r3wa, wrdt => r3wd);

		mux:   process(     clk,
		                    rda0, rda1, rda2, rda3,
		                    r0rd, r1rd, r2rd, r3rd,
		                    wra0, wra1, wra2, wra3,
		                    dti0Reg, dti1Reg, dti2Reg, dti3Reg) is
		   begin
		       if clk = '0' then
		           
		            case rda0(1 downto 0) is
		              when "00" =>
		                 dto0 <= r0rd;
		              when "01" =>
		                 dto0 <= r1rd;
		              when "10" =>
		                 dto0 <= r2rd;
		              when others =>
		                 dto0 <= r3rd; 
		           end case;
		           --
		            case rda1(1 downto 0) is
		              when "00" =>
		                 dto1 <= r0rd;
		              when "01" =>
		                 dto1 <= r1rd;
		              when "10" =>
		                 dto1 <= r2rd;
		              when others =>
		                 dto1 <= r3rd; 
		           end case;
		           --
		           case rda2(1 downto 0) is
		              when "00" =>
		                 dto2 <= r0rd;
		              when "01" =>
		                 dto2 <= r1rd;
		              when "10" =>
		                 dto2 <= r2rd;
		              when others =>
		                 dto2 <= r3rd; 
		           end case;
		           --
		           case rda3(1 downto 0) is
		              when "00" =>
		                 dto3 <= r0rd;
		              when "01" =>
		                 dto3 <= r1rd;
		              when "10" =>
		                 dto3 <= r2rd;
		              when others =>
		                 dto3 <= r3rd; 
		           end case;
		       end if;
		
		end process mux;
		
		r0ra <= rda0(rda0'left downto 2) when std_logic_vector(rda0(1 downto 0))=c00 else
		        rda1(rda1'left downto 2) when std_logic_vector(rda1(1 downto 0))=c00 else
		        rda2(rda2'left downto 2) when std_logic_vector(rda2(1 downto 0))=c00 else
		        rda3(rda2'left downto 2);
		        
	   r1ra <= rda0(rda0'left downto 2) when std_logic_vector(rda0(1 downto 0))=c01 else
		        rda1(rda1'left downto 2) when std_logic_vector(rda1(1 downto 0))=c01 else
		        rda2(rda2'left downto 2) when std_logic_vector(rda2(1 downto 0))=c01 else
		        rda3(rda2'left downto 2);

		r2ra <= rda0(rda0'left downto 2) when std_logic_vector(rda0(1 downto 0))=c10 else
		        rda1(rda1'left downto 2) when std_logic_vector(rda1(1 downto 0))=c10 else
		        rda2(rda2'left downto 2) when std_logic_vector(rda2(1 downto 0))=c10 else
		        rda3(rda2'left downto 2);
		        
		r3ra <= rda0(rda0'left downto 2) when std_logic_vector(rda0(1 downto 0))=c11 else
		        rda1(rda1'left downto 2) when std_logic_vector(rda1(1 downto 0))=c11 else
		        rda2(rda2'left downto 2) when std_logic_vector(rda2(1 downto 0))=c11 else
		        rda3(rda2'left downto 2);
		        
		r0wa <= wra0(wra0'left downto 2) when std_logic_vector(wra0(1 downto 0))=c00 else
		        wra1(wra1'left downto 2) when std_logic_vector(wra1(1 downto 0))=c00 else
		        wra2(wra2'left downto 2) when std_logic_vector(wra2(1 downto 0))=c00 else
		        wra3(wra3'left downto 2); 
		        
		r0wd <= dti0Reg when std_logic_vector(wra0(1 downto 0))=c00 else
		        dti1Reg when std_logic_vector(wra1(1 downto 0))=c00 else
		        dti2Reg when std_logic_vector(wra2(1 downto 0))=c00 else
		        dti3Reg;
		 
		r1wa <= wra0(wra0'left downto 2) when std_logic_vector(wra0(1 downto 0))=c01 else
		        wra1(wra1'left downto 2) when std_logic_vector(wra1(1 downto 0))=c01 else
		        wra2(wra2'left downto 2) when std_logic_vector(wra2(1 downto 0))=c01 else
		        wra3(wra3'left downto 2); 
		        
		r1wd <= dti0Reg when std_logic_vector(wra0(1 downto 0))=c01 else
		        dti1Reg when std_logic_vector(wra1(1 downto 0))=c01 else
		        dti2Reg when std_logic_vector(wra2(1 downto 0))=c01 else
		        dti3Reg;
		
		r2wa <= wra0(wra0'left downto 2) when std_logic_vector(wra0(1 downto 0))=c10 else
		        wra1(wra1'left downto 2) when std_logic_vector(wra1(1 downto 0))=c10 else
		        wra2(wra2'left downto 2) when std_logic_vector(wra2(1 downto 0))=c10 else
		        wra3(wra3'left downto 2); 
		        
		r2wd <= dti0Reg when std_logic_vector(wra0(1 downto 0))=c10 else
		        dti1Reg when std_logic_vector(wra1(1 downto 0))=c10 else
		        dti2Reg when std_logic_vector(wra2(1 downto 0))=c10 else
		        dti3Reg;
		        
		r3wa <= wra0(wra0'left downto 2) when std_logic_vector(wra0(1 downto 0))=c11 else
		        wra1(wra1'left downto 2) when std_logic_vector(wra1(1 downto 0))=c11 else
		        wra2(wra2'left downto 2) when std_logic_vector(wra2(1 downto 0))=c11 else
		        wra3(wra3'left downto 2); 
		        
		r3wd <= dti0Reg when std_logic_vector(wra0(1 downto 0))=c11 else
		        dti1Reg when std_logic_vector(wra1(1 downto 0))=c11 else
		        dti2Reg when std_logic_vector(wra2(1 downto 0))=c11 else
		        dti3Reg;
		----
	end architecture;