fftoutbuf.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;
	
	
entity fftOutBuf is
    generic(
				Aw : natural := Addrw;
				Dw : natural := pstDw
			);
	 port(
	      rst : in std_logic;
	     
	      extclk, 
	      inclk : in std_logic;
			--
			inEn : in std_logic;
			dti0, dti1, dti2, dti3: in slvDt;
			
			
			outDt: out slvDt;
			
			dtvld : out std_logic
			
			
	 );
end entity fftOutBuf;

architecture bhv of fftOutBuf is
       constant c1 : slvBRAddrt := (others => '1');
       constant c0 : slvBRAddrt := (others => '0');
       constant slvaddrt1 : slvAddrt := (others => '1');
       
       constant c00 : std_logic_vector(1 downto 0) := "00";
       constant c01 : std_logic_vector(1 downto 0) := "01";
       constant c10 : std_logic_vector(1 downto 0) := "10";
       constant c11 : std_logic_vector(1 downto 0) := "11";
        
       --signal dtArr : std_logic;  
       
       signal rDti0, rDti1, rDti2, rDti3 : slvDt;
       signal dto0, dto1, dto2, dto3: slvDt;     

       signal wren: std_logic_vector(3 downto 0);
       signal waddr : slvBRAddrt;
       signal cnti: slvBRAddrt; 
       signal wa : slvBRAddrt;
       signal raddr : slvBRAddrt;
       
       signal rda : slvAddrt;
       signal cnto: slvAddrt;
       signal ostart : std_logic;
       
       signal rdto : slvDt;
       

    begin                 
              
  		ram0:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => inclk, rda => raddr, rddt => dto0,
                    wren => inEn, wra => wa, wrdt => rDti0);
      ram1:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => inclk, rda => raddr, rddt => dto1,
                    wren => inEn, wra => wa, wrdt => rDti1);
      ram2:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => inclk, rda => raddr, rddt => dto2,
                    wren => inEn, wra => wa, wrdt => rDti2);
      ram3:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => inclk, rda => raddr, rddt => dto3,
                    wren => inEn, wra => wa, wrdt => rDti3);
    
      wrData : process (rst, inclk) is
            
         begin
             if rst = '1' then
                ostart <= '0';
                cnti <= (others => '0'); 
                wa <= (others => '0');
                rDti0 <= (others => '0');
                rDti1 <= (others => '0');
                rDti2 <= (others => '0');
                rDti3 <= (others => '0');
             elsif rising_edge(inclk) then
                if inEn = '1' then
                    rDti0 <= dti0;
                    rDti1 <= dti1;
                    rDti2 <= dti2;
                    rDti3 <= dti3;
                    
                    cnti <= cnti + 1;
                    wa <= cnti;
                    
                end if;
                
                if cnti = c1 then
                    ostart <= '1';
                elsif rda = slvaddrt1 then
                    ostart <= '0';
                end if;
             end if;
         end process wrData;
         
      oData : process (rst, extclk) is
         begin
             if rst = '1' then
                 --rda <= (others => '0');
                 cnto <= (others => '0');
             elsif rising_edge(extclk) then
                 if ostart = '1' then
                    cnto <= cnto + 1;
                    --rda <= rda +1;
                 end if;
                 dtvld <= ostart;
             end if;
         end process oData;
       
      rda <= cnto(1 downto 0) & cnto(3 downto 2) & cnto(5 downto 4) & cnto(7 downto 6);
       
      raddr <= slvBRAddrt(rda(rda'left downto 2));
      
      rdto <= dto0 when std_logic_vector(rda(1 downto 0)) = c00 else
               dto1 when std_logic_vector(rda(1 downto 0)) = c01 else
               dto2 when std_logic_vector(rda(1 downto 0)) = c10 else
               dto3;
               
       oReg: process(rst, extclk) is
          begin
              if rst = '1' then
                  outDt <= (others => '0');
              elsif rising_edge(extclk) then
                  outDt <= rdto;
              end if;
          end process oReg;
      
         
     
      
    end architecture bhv;