fftinbuf.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;
	
	
entity fftInBuf is
    generic(
				Aw : natural := Addrw;
				Dw : natural := pstDw
			);
	 port(
	      rst : in std_logic;
	      
	      extclk, 
	      inclk : in std_logic;
			--
			inEn : in std_logic;
			--
			--inrdy : out std_logic;
			
			outrdy : in std_logic;
			inDt: in slvDt;
			
			dto0, dto1, dto2, dto3: out slvDt;
			
			bufemptyN : out std_logic
			--cnti: in slvAddrt
	 );
end entity fftInBuf;

architecture bhv of fftInBuf is
       constant c1 : slvBRAddrt := (others => '1');
       constant c0 : slvBRAddrt := (others => '0');
        
       --signal dtArr : std_logic;     

       signal wren: std_logic_vector(3 downto 0);
       signal waddr : slvBRAddrt;
       signal cnti: slvAddrt; 
       signal ra : slvBRAddrt;
       
       signal bufempty : std_logic; 
    begin
        
     
  		ram0:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => inclk, rda => ra, rddt => dto0,
                    wren => wren(0), wra => waddr, wrdt => inDt);
      ram1:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => inclk, rda => ra, rddt => dto1,
                    wren => wren(1), wra => waddr, wrdt => inDt);
      ram2:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => inclk, rda => ra, rddt => dto2,
                    wren => wren(2), wra => waddr, wrdt => inDt);
      ram3:   entity work.fftBRam (behavior)
              generic map (Depth => 2**(Addrw -2))
              port map( clk => inclk, rda => ra, rddt => dto3,
                    wren => wren(3), wra => waddr, wrdt => inDt);
      
      wrAddrGnr: process(rst, extclk) is
         begin
            if(rst = '1') then
                --dtArr <= '0';
                cnti <= (others => '0');
            elsif rising_edge(extclk) then
                if(inEn = '1') then
                    cnti <= cnti + 1;
                end if;
                --dtArr <= inEn;
            end if;
         end process wrAddrGnr;
      
      dstrWrAddr: process(extclk) is
         begin
             if rising_edge(extclk) then
                  --wren <= (conv_integer(cnti(1 downto 0)) => inEn, others => '0');
					   case cnti(1 downto 0) is
						   when "00" =>
							   wren <= "0001";
						   when "01" =>
							   wren <= "0010";
						   when "10" =>
							   wren <= "0100";
						   when others =>
							   wren <= "1000";
					    end case;
                waddr <= cnti(cnti'left downto 2);
             end if;
        end process  dstrWrAddr;
      
      rAddrGnr : process (rst, inclk) is
         begin
             if(rst = '1') then
                bufemptyN <= '0';
                ra <= (others => '0');
            elsif rising_edge(inclk) then
                if(outrdy = '1') then
                    ra <= ra + 1;
                    if ra = c1 then 
                       bufemptyN <= inEn;
                    end if;
                end if;
            end if;
         end process rAddrGnr;
         
     
      
    end architecture bhv;