fftaddrlgc.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	
library work;
	use work.fftDef.all;	
	
entity fftAddrLgc is
    port(
           cnti : in slvAddrt;
           sctrl : in slvSct;
           idx   : in std_logic_vector(1 downto 0); 
           addro : out slvAddrt
          );
end entity fftAddrLgc;

architecture behavior of fftAddrLgc is
    function genAddr(cnti : in slvAddrt; sctrl : in slvSct; 
							idx : in std_logic_vector(1 downto 0) ) 
					return slvAddrt is
			--	[2n+1][2n] [2n-1][2n-2] ... [3][2] [1][0] ---------cnti
			--        |          |             |      |
			--       [n]       [n-1]          [1]    [0]  ---------sctrl
			--        | _______/0|1_____...__/0|1___/0|1
			--        |/         |/            |/     |
			--  [2n+1][2n] [2n-1][2n-2] ... [3][2] [1][0] ---------addrs
					variable addro : slvAddrt;
				begin
					--for i in 0 to sctrl'left  loop --'
					--	if i=0 then
					--		for j in 0 to 1 loop
					--			addro(i*2+j) := (cnti(i*2+j) and (not sctrl(i))) or
					--							(idx(j) and sctrl(i));
					--		end loop;
					--	else
					--		for j in 0 to 1 loop
					--			addro(i*2+j) := (cnti(i*2+j) and (not sctrl(i))) or
					--							 (cnti((i-1)*2+j) and sctrl(i-1)) or
					--			 				(idx(j) and (sctrl(i) xor sctrl(i-1)));
					--		end loop;
					--	end if;
					--end loop;
					case sctrl is
						when "1000" =>--"1000" =>
							addro := unsigned(idx & std_logic_vector(cnti(cnti'left -2 downto 0)));
						when "0100" =>--"1100" =>
							addro := unsigned(std_logic_vector(cnti(cnti'left -2 downto cnti'left -4 +1)) & idx & std_logic_vector(cnti(cnti'left -4 downto 0)));
						when "0010" =>--"1110" =>
							addro := unsigned(std_logic_vector(cnti(cnti'left -2 downto cnti'left -6 +1)) & idx & std_logic_vector(cnti(cnti'left -6 downto 0)));
						when "0001" =>--"1111" =>
						   addro := unsigned(std_logic_vector(cnti(cnti'left -2 downto 0)) & idx) ;
						when others =>
							addro := (others => '0');
					end case;
					return addro;	
				end function genAddr;
		function avdCflct(addri : in slvAddrt) return slvAddrt is --to avoid address conflict
		      variable r : slvAddrt;
		   begin
		       r := addri;
		       for i in 1 to (r'left-1)/2 loop
		          r(0) := r(0) xor r(2*i); --r(2) xor r(4) xor r(6);
		          r(1) := r(1) xor r(2*i +1); --xor r(5) xor r(7);
		       end loop;
		      -- return addri(addri'left downto 2) &
		      --        (addri(1) xor addri(3) xor addri(5) xor addri(7))&
		      --       (addri(0) xor addri(2) xor addri(4) xor addri(6));
		      return r;
		   end function avdCflct; 
		   signal tmp : slvAddrt;
    begin
        tmp <= genAddr(cnti, sctrl, idx);
        addro <= avdCflct(tmp);
end architecture behavior;