fftcoeflgc.vhd

来自「基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256」· VHDL 代码 · 共 71 行

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	
library work;
	use work.fftDef.all;	

entity fftCoeflgc is
	port(
			cnti : in slvAddrt; 
			sctrl : in slvSct;
			coefko : out slvAddrt
		);
end fftCoeflgc;

architecture Behavioral of fftCoeflgc is
	 function genCoefk(cnti : in slvAddrt; sctrl : in slvSct) 
					return slvAddrt is
					variable coefko : slvAddrt;
					variable coefko0, coefko1, coefko2 : slvAddrt;
				begin
--					for i in sctrl'left  downto 0 loop --'
--						if i =  sctrl'left then --'
--							coefko := cnti;
--						else
--							if sctrl(i) = '1' then
--								coefko := coefko(coefko'left -2 downto 0) & "00"; --'
--							else
--								coefko := coefko;
--							end if;
--						end if;
--					end loop;
--					--
--					coefko(coefko'left downto coefko'left -1) := "00";
--					--
					coefko0 := "00"&cnti(cnti'left -2 downto 0);
		         coefko1 := "00"&cnti(cnti'left -4 downto 0)&"00";
		         coefko2 := "00"&cnti(cnti'left -6 downto 0)&"0000";

					case sctrl is
						when "1000" =>--"1000" =>
							coefko := coefko0;
						when "0100" =>--"1100" =>
							coefko := coefko1;
						when "0010" =>--"1110" =>
							coefko := coefko2;
						when others =>
							coefko := (others => '0');
					end case;
					return coefko;
				end function genCoefk;

		signal coefko0, coefko1, coefko2 : slvAddrt;
	begin
		coefko <= genCoefk(cnti,sctrl);
		--
		--coefko0 <= "00"&cnti(cnti'left -2 downto 0);
		--coefko1 <= "00"&cnti(cnti'left -4 downto 0)&"00";
		--coefko2 <= "00"&cnti(cnti'left -6 downto 0)&"0000";
		--
		--coefko <= 	coefko0 when sctrl = "1000" else
		--			coefko1 when sctrl = "1100" else
		--			coefko2 when sctrl = "1110" else
		--			(others => '0');
end Behavioral;