ffttestbench.without buf.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;
	use ieee.std_logic_textio.all;
	
library std;
    use std.textio.all;
	
library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;

entity fftTestBench is
    generic(
             period : time := 10 ns;
             saveresult : boolean := true
             );
end entity fftTestBench;

architecture behavior of fftTestBench is
       signal clk : std_logic:= '1';
       signal rst : std_logic:= '1';
       signal start : std_logic := '0';
       ---
       signal dtvld : std_logic;
       signal dto0, dto1, dto2, dto3 : slvDt;
       ---
       signal inrdy : std_logic;
       signal dti0, dti1, dti2, dti3 : slvDt;
       
       signal agucnto : slvAddrt;
       signal bufin : slvDt;
    begin
        --
        inbuftest: entity work.fftInBuf (bhv)
                    port map(rst => rst, inclk => clk,
                     extclk => clk,
                     inEn => start,
                     --
                     outrdy => inrdy,
                     --
                     inDt => bufin );
      readinbuf: process(clk, inrdy) is
			file vecinfile : text open read_mode is "fftInput2.vec";
			variable vecline : line;
			 variable dtre, dtim : std_logic_vector(DataWidth -1 downto 0);
       begin
          if start = '1' then
              if clk = '1' then
						if not endfile(vecinFile) then
						readline( vecinFile, vecLine);
						read(vecLine, dtre);
						
						read(vecLine, dtim);
						bufin <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
						--dtre := unsigned(dtre) + 1;
						
					end if;
              end if;
           else
               dtre := (others => '0');
           end if;
       end process readinbuf;
        --
        
    waveform:   process is
       begin
          wait for period/2;
          clk <= not clk;
          -- reset
          if now < 20 ns then
             rst <= '1';
          else
             rst <= '0';
          end if;
          -- start
          if now < 40 ns or now > 7000 ns then
             start <= '0';
          else
             start <= '1';
          end if;
       end process waveform;
    
    processor:   entity work.fftp (structure) 
        port map(rst =>rst, clk => clk, start => start,
                 outvld => dtvld,
                 vldDt0 => dto0, vldDt1 => dto1, vldDt2 => dto2, vldDt3 => dto3,
                 inrdy => inrdy,
                 inDt0 => dti0, inDt1 => dti1, inDt2 => dti2, inDt3 => dti3,
                 --
                 agucnto => agucnto);
    
    readin: process(clk, inrdy) is
			file vecinfile : text open read_mode is "fftInput.vec";
			variable vecline : line;
			 variable dtre, dtim : std_logic_vector(DataWidth -1 downto 0);
       begin
          if inrdy = '1' then
              if clk = '0' then
						if not endfile(vecinFile) then
						readline( vecinFile, vecLine);
						read(vecLine, dtre);
						read(vecLine, dtim);
						dti0 <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
						
						readline( vecinFile, vecLine);
						read(vecLine, dtre);
						read(vecLine, dtim);
						dti1 <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
						
						readline( vecinFile, vecLine);
						read(vecLine, dtre);
						read(vecLine, dtim);
						dti2 <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
						
						readline( vecinFile, vecLine);
						read(vecLine, dtre);
						read(vecLine, dtim);
						dti3 <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
						
					end if;
              end if;
          else
             
          end if;  
       end process readin;             
    
    saveout:   process(clk, dtvld, dto0, dto1, dto2, dto3) is
          file savefile : text open write_mode is "dataout.vec";
          variable txtline : line;
       begin
           if saveresult and dtvld = '1' then
               if rising_edge(clk) then
                   write(txtline, signedToReal(DtGetRe(dto0),DataWidth));
                   write(txtline, ' ');
                   write(txtline, signedToReal(DtGetIm(dto0),DataWidth));

                   writeline(savefile, txtline);
                   
                   write(txtline, signedToReal(DtGetRe(dto1),DataWidth));

                   write(txtline, ' ');
                   write(txtline, signedToReal(DtGetIm(dto1),DataWidth));

                   writeline(savefile, txtline);
                   
                   write(txtline, signedToReal(DtGetRe(dto2),DataWidth));

                   write(txtline, ' ');
                   write(txtline, signedToReal(DtGetIm(dto2),DataWidth));

                   writeline(savefile, txtline);
                   
                   write(txtline, signedToReal(DtGetRe(dto3),DataWidth));

                   write(txtline, ' ');
                   write(txtline, signedToReal(DtGetIm(dto3),DataWidth));

                   writeline(savefile, txtline);
               end if;
           end if;
       end process saveout;
    end architecture behavior;