fftp.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;
	
entity fftP is
	generic(
				Aw : natural := Addrw;
				Dw : natural := pstDw;
				Rdx : natural := fftRdx;
				ifft : boolean := false
			);
	port(
			clk, extclk, rst : in std_logic;
			--
			start : in std_logic;
			finish : out std_logic;
			
			dtvld : out std_logic;
			dto :out slvDt;
			inDt : in slvDt
		);
end entity fftP;

architecture structure of fftP is
      signal outvld : std_logic;
      signal vldDt0, vldDt1, vldDt2, vldDt3 : slvDt;
      signal inDt0, inDt1, inDt2, inDt3 : slvDt;
      signal inrdy : std_logic;
      
		signal agufin, aguen, rden: std_logic;
		signal addr0, addr1, addr2, addr3, coefko : slvAddrt;
		signal rda0, rda1, rda2, rda3 :  slvAddrt;
		signal wra0, wra1, wra2, wra3 :  slvAddrt;
		signal wren : std_logic;
		signal rddt0, rddt1, rddt2, rddt3 : slvDt;
		signal crdt0, crdt1, crdt2, crdt3 : slvDt;
		signal wrdt0, wrdt1, wrdt2, wrdt3 : slvDt;
		signal coren : std_logic;
		signal lastpass : std_logic;
		signal bInrdy : std_logic;
		signal bufemptyN : std_logic;
		signal soutVld : std_logic;
	begin
	    
	inbuf: entity work.fftInBuf (bhv)
                    port map(rst => rst, inclk => clk,
                     extclk => extclk,
                     inEn => start,
                     --
                     outrdy => inrdy,
                     --
                     dto0 => inDt0, dto1 => inDt1, 
                     dto2 => inDt2, dto3 => inDt3,
                     --
                     inDt => inDt,
                     bufemptyN => bufemptyN );
                     
    outbuf:  entity work.fftoutBuf(bhv)
	     port map( rst => rst,
	              extclk => extclk, inclk => clk,	
	              inEn => outvld,
	              dti0 => vldDt0, dti1 => vldDt1, dti2 => vldDt2, dti3 => vldDt3,
	              outDt => dto,
			        dtvld => dtvld
			         );

                     
	PLCTRL:	entity work.fftPLL (std_behavior)
			port map(	rst => rst, clk => clk, agufin => agufin, start => start,
						plfin => finish, aguen => aguen, rden => rden, coren => coren);
	---	
	AGU:	entity work.fftAgu (std_behavior)
			port map( 	clk => clk, rst => rst, enable => aguen,
						finish => agufin, 
						lastpass => lastpass,
						ado0 => addr0, ado1 => addr1, ado2 => addr2, ado3 => addr3,
						coefko => coefko );
	---
	AddrFifo:
			entity work.fftFiFo (behavior) --generic map ( plDel : natural := plsts -2);
			port map( 	clk => clk,
						addri0 => addr0, addri1=> addr1, addri2=> addr2, addri3=> addr3,
						enable => rden,
						rda0 => rda0, rda1 => rda1, rda2 => rda2, rda3 => rda3,
						wra0 => wra0, wra1 => wra1, wra2 => wra2, wra3 => wra3,
						wren => wren);
	---
	Mem:	entity work.fftMem (behavior)
			port map(	clk => clk,
						rda0 => rda0, rda1 => rda1, rda2 => rda2, rda3 => rda3,
						dto0 => rddt0, dto1 => rddt1, dto2 => rddt2, dto3 => rddt3,
						wra0 => wra0, wra1 => wra1, wra2 => wra2, wra3 => wra3,
						wren => wren,
						dti0 => wrdt0, dti1 => wrdt1, dti2 => wrdt2, dti3 => wrdt3);	
	---
	Core:	entity work.fftCore (std_structure)
	      generic map(ifft => ifft)
			port map(	rst => rst ,clk => clk, coefk1 => coefko,
						enable => coren,
						lastpass => lastpass,
						dti0 => rddt0, dti1 => rddt1, dti2 => rddt2, dti3 => rddt3,
						dto0 => crdt0, dto1 => crdt1, dto2 => crdt2, dto3 => crdt3,
						--
						inrdy => bInrdy,
						--output
						outvld => soutvld);
		vldDt0 <= crdt0; 
		vldDt1 <= crdt1;
		vldDt2 <= crdt2;
		vldDt3 <= crdt3;
		
		ovldSys: process (clk) is
		   begin
		       if falling_edge(clk) then
		          outvld <= soutvld and bufemptyN;
		       end if;
		   end process ovldSys;
	---
	inrdy <= bInrdy;
	---
	--latch: process(clk, bInrdy,
	--				crdt0, crdt1, crdt2, crdt3,
	--				indt0, indt1, indt2, indt3) is
	--	begin
	--		if clk = '0' then
	--			case bInrdy is
	--				when '1' 
						wrdt0 <= indt0 when bInrdy = '1' else crdt0;
						wrdt1 <= indt1 when bInrdy = '1' else crdt1;
						wrdt2 <= indt2 when bInrdy = '1' else crdt2;
						wrdt3 <= indt3 when bInrdy = '1' else crdt3;
	--		end if;
	--	end process latch;
	---	
	end architecture structure;