coretest.vhd

基于存储器的基4按频率抽取的fft 的vhdl描述 可以对连续数据流进行256点的fft

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-- Company: 
-- Engineer:
--
-- Create Date:   13:55:33 05/12/2007
-- Design Name:   fftCore
-- Module Name:   G:/ether/xlxfft/CoreTest.vhd
-- Project Name:  xlxfft
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: fftCore
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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library ieee;
	use ieee.std_logic_1164.all;
	use IEEE.std_logic_arith.all;
	use ieee.std_logic_textio.all;
--
	use IEEE.math_real.all;
	use IEEE.math_complex.all;

library std;
	use std.standard.all;
    use std.textio.all;
	 --
library work;
	use work.fftDef.all;	
	--
	use work.fftDataType.all;
	

ENTITY CoreTest_vhd IS
END CoreTest_vhd;

ARCHITECTURE behavior OF CoreTest_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT fftCore
	PORT(
		rst : in std_logic;
		clk : in std_logic;
		coefk1 : in slvAddrt;
		enable : in std_logic;
		lastpass : in std_logic;
		dti0, dti1, dti2, dti3 : in slvDt;          
		dto0, dto1, dto2, dto3 : out slvDt;
		inrdy : out std_logic;
		outvld : out std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL rst :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL enable :  std_logic := '0';
	SIGNAL lastpass :  std_logic := '0';
	SIGNAL dti0, dti1, dti2, dti3 :  slvDt;
	--
	
	SIGNAL coefk1 :  slvAddrt := (others => '0');
	constant slvAddrtZero : slvAddrt := (others => '0');
	--Outputs
	SIGNAL dto0, dto1, dto2, dto3 :  slvDt;
	--
	SIGNAL inrdy :  std_logic;
	SIGNAL outvld :  std_logic;
	--
	signal dti0Reg, dti1Reg, dti2Reg, dti3Reg : slvDt;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: fftCore PORT MAP(
		rst => rst,
		clk => clk,
		coefk1 => coefk1,
		enable => enable,
		lastpass => lastpass,
		dti0 => dti0,
		dti1 => dti1,
		dti2 => dti2,
		dti3 => dti3,
		dto0 => dto0,
		dto1 => dto1,
		dto2 => dto2,
		dto3 => dto3,
		inrdy => inrdy,
		outvld => outvld
	);
		
	waveform : process is
		begin
			
			
         -- reset
         if now < 20 ns then
            rst <= '1';
         else
            rst <= '0';
         end if;
         --
			-- 
         if now < 40 ns or now > 7000 ns then
            enable <= '0';
				lastpass <= '0';
         else
				lastpass <= '1';
				enable <= '1';
         end if;
			wait for 10 ns/2;
         clk <= not clk;
		end process waveform;
		
	wavein : process(clk) is
			file vecinFile : text open read_mode is "CoreTestInb.vec"; 
			variable vecline : line;
			variable icoefk1 : integer;
			variable dtre, dtim : std_logic_vector(DataWidth -1 downto 0);
		begin
			if falling_edge(clk) then
				if enable = '1' then
					if not endfile(vecinFile) then
						readline( vecinFile, vecLine); 
						read(vecLine, icoefk1);
						coefk1 <= slvAddrtZero + icoefk1;
						--
						read(vecLine, dtre);
						read(vecLine, dtim);
						dti0Reg <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
						
						--
						read(vecLine, dtre);
						read(vecLine, dtim);
						dti1Reg <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
						
						--
						read(vecLine, dtre);
						read(vecLine, dtim);
						dti2Reg <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
						
						--
						read(vecLine, dtre);
						read(vecLine, dtim);
						dti3Reg <= CreateDt(slvDtSub(dtre), slvDtSub(dtim));
					end if;
					dti0 <= dti0Reg;
					dti1 <= dti1Reg;
					dti2 <= dti2Reg;
					dti3 <= dti3Reg;
				end if;
			end if;
		end process wavein;
		
	waveout : process(clk) is
		file vecOutFile : text open read_mode is "CoreTestOutb.vec"; 
		file errorOutFile : text open write_mode is "CoreTesterrorOut.txt"; 
			variable err : real;
			variable vecline, errorline : line;
			variable dtre, dtim : std_logic_vector(DataWidth -1 downto 0);
		begin
			if rising_edge(clk) then
				if outvld = '1' then
					if not endfile(vecOutFile) then
						readline(vecOutFile, vecLine); 
						--
						read(vecLine, dtre);
						read(vecLine, dtim);
						assert (
								abs(DttoComplex(CreateDt(slvDtSub(dtre), slvDtSub(dtim)))- DttoComplex(dto0))< 2.0e-4
							)--abs(dtre - dto0.re) < 1.0e-9) and (abs(dtim - dto0.im) < 1.0e-9)
							report "dto0 error too large!"
							severity warning;
						
						write(errorLine,abs(DttoComplex(CreateDt(slvDtSub(dtre), slvDtSub(dtim)))- DttoComplex(dto0)));
						writeline(errorOutFile,errorLine);
						write(errorLine,dto0);
						writeline(errorOutFile,errorLine);
						write(errorLine, dtre&dtim);
						writeline(errorOutFile,errorLine);
						write(errorLine, ' ');
						writeline(errorOutFile,errorLine);
						--
						read(vecLine, dtre);
						read(vecLine, dtim);
						assert (
							abs(DttoComplex(CreateDt(slvDtSub(dtre), slvDtSub(dtim)))- DttoComplex(dto1))< 2.0e-4	
							)
							report "dto1 error too large!"
							severity warning;
							
						write(errorLine,abs(DttoComplex(CreateDt(slvDtSub(dtre), slvDtSub(dtim)))- DttoComplex(dto1)));
						writeline(errorOutFile,errorLine);
						write(errorLine,dto1);
						writeline(errorOutFile,errorLine);
						write(errorLine, dtre&dtim);
						writeline(errorOutFile,errorLine);
						write(errorLine, ' ');
						writeline(errorOutFile,errorLine);
						--
						read(vecLine, dtre);
						read(vecLine, dtim);
						assert (
							abs(DttoComplex(CreateDt(slvDtSub(dtre), slvDtSub(dtim)))- DttoComplex(dto2))< 2.0e-4	
							)report "dto2 error too large!"
							severity warning;
							
						write(errorLine,abs(DttoComplex(CreateDt(slvDtSub(dtre), slvDtSub(dtim)))- DttoComplex(dto2)));
						writeline(errorOutFile,errorLine);
						write(errorLine,dto2);
						writeline(errorOutFile,errorLine);
						write(errorLine, dtre&dtim);
						writeline(errorOutFile,errorLine);
						write(errorLine, ' ');
						writeline(errorOutFile,errorLine);
						--
						read(vecLine, dtre);
						read(vecLine, dtim);
						assert (
							abs(DttoComplex(CreateDt(slvDtSub(dtre), slvDtSub(dtim)))- DttoComplex(dto3))< 2.0e-4	
							)report "dto3 error too large!"
							severity warning;
						
						write(errorLine,abs(DttoComplex(CreateDt(slvDtSub(dtre), slvDtSub(dtim)))- DttoComplex(dto3)));
						writeline(errorOutFile,errorLine);
						write(errorLine,dto3);
						writeline(errorOutFile,errorLine);
						write(errorLine, dtre&dtim);
						writeline(errorOutFile,errorLine);
						write(errorLine, ' ');
						writeline(errorOutFile,errorLine);
						
						writeline(errorOutFile,errorLine);	
					end if;
				end if;
			end if;
		end process waveout;
END;